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[/] [claw/] [trunk/] [or1200_cpu/] [or1200_mem2reg.v] - Blame information for rev 4

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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  OR1200's mem2reg alignment                                  ////
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////                                                              ////
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////  This file is part of the OpenRISC 1200 project              ////
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////  http://www.opencores.org/cores/or1k/                        ////
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////                                                              ////
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////  Description                                                 ////
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////  Two versions of Memory to register data alignment.          ////
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////                                                              ////
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////  To Do:                                                      ////
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////   - make it smaller and faster                               ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Damjan Lampret, lampret@opencores.org                 ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
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// Revision 1.5  2002/09/03 22:28:21  lampret
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// As per Taylor Su suggestion all case blocks are full case by default and optionally (OR1200_CASE_DEFAULT) can be disabled to increase clock frequncy.
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//
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// Revision 1.4  2002/03/29 15:16:56  lampret
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// Some of the warnings fixed.
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//
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// Revision 1.3  2002/03/28 19:14:10  lampret
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// Changed define name from OR1200_MEM2REG_FAST to OR1200_IMPL_MEM2REG2
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//
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// Revision 1.2  2002/01/14 06:18:22  lampret
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// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
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//
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// Revision 1.1  2002/01/03 08:16:15  lampret
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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//
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// Revision 1.9  2001/10/21 17:57:16  lampret
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// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
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//
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// Revision 1.8  2001/10/19 23:28:46  lampret
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// Fixed some synthesis warnings. Configured with caches and MMUs.
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//
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// Revision 1.7  2001/10/14 13:12:09  lampret
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// MP3 version.
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//
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// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
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// no message
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//
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// Revision 1.2  2001/08/09 13:39:33  lampret
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// Major clean-up.
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//
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// Revision 1.1  2001/07/20 00:46:03  lampret
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// Development version of RTL. Libraries are missing.
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//
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//
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82
// synopsys translate_off
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`include "timescale.v"
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// synopsys translate_on
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`include "or1200_defines.v"
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87
module or1200_mem2reg(addr, lsu_op, memdata, regdata);
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89
parameter width = 32; // `OR1200_OPERAND_WIDTH;         // bviyer
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91
//
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// I/O
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//
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input   [1:0]                    addr;
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input   [`OR1200_LSUOP_WIDTH-1:0]        lsu_op;
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input   [width-1:0]              memdata;
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output  [width-1:0]              regdata;
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//
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// In the past faster implementation of mem2reg (today probably slower)
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//
103
`ifdef OR1200_IMPL_MEM2REG2
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`define OR1200_M2R_BYTE0 4'b0000
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`define OR1200_M2R_BYTE1 4'b0001
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`define OR1200_M2R_BYTE2 4'b0010
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`define OR1200_M2R_BYTE3 4'b0011
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`define OR1200_M2R_EXTB0 4'b0100
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`define OR1200_M2R_EXTB1 4'b0101
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`define OR1200_M2R_EXTB2 4'b0110
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`define OR1200_M2R_EXTB3 4'b0111
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`define OR1200_M2R_ZERO  4'b0000
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reg     [7:0]                    regdata_hh;
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reg     [7:0]                    regdata_hl;
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reg     [7:0]                    regdata_lh;
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reg     [7:0]                    regdata_ll;
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reg     [width-1:0]              aligned;
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reg     [3:0]                    sel_byte0, sel_byte1,
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                                sel_byte2, sel_byte3;
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123
assign regdata = {regdata_hh, regdata_hl, regdata_lh, regdata_ll};
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125
//
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// Byte select 0
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//
128
always @(addr or lsu_op) begin
129
        casex({lsu_op[2:0], addr})       // synopsys parallel_case
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                {3'b01x, 2'b00}:                        // lbz/lbs 0
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                        sel_byte0 = `OR1200_M2R_BYTE3;  // take byte 3
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                {3'b01x, 2'b01},                        // lbz/lbs 1
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                {3'b10x, 2'b00}:                        // lhz/lhs 0
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                        sel_byte0 = `OR1200_M2R_BYTE2;  // take byte 2
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                {3'b01x, 2'b10}:                        // lbz/lbs 2
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                        sel_byte0 = `OR1200_M2R_BYTE1;  // take byte 1
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                default:                                // all other cases
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                        sel_byte0 = `OR1200_M2R_BYTE0;  // take byte 0
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        endcase
140
end
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142
//
143
// Byte select 1
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//
145
always @(addr or lsu_op) begin
146
        casex({lsu_op[2:0], addr})       // synopsys parallel_case
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                {3'b010, 2'bxx}:                        // lbz
148
                        sel_byte1 = `OR1200_M2R_ZERO;   // zero extend
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                {3'b011, 2'b00}:                        // lbs 0
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                        sel_byte1 = `OR1200_M2R_EXTB3;  // sign extend from byte 3
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                {3'b011, 2'b01}:                        // lbs 1
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                        sel_byte1 = `OR1200_M2R_EXTB2;  // sign extend from byte 2
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                {3'b011, 2'b10}:                        // lbs 2
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                        sel_byte1 = `OR1200_M2R_EXTB1;  // sign extend from byte 1
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                {3'b011, 2'b11}:                        // lbs 3
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                        sel_byte1 = `OR1200_M2R_EXTB0;  // sign extend from byte 0
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                {3'b10x, 2'b00}:                        // lhz/lhs 0
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                        sel_byte1 = `OR1200_M2R_BYTE3;  // take byte 3
159
                default:                                // all other cases
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                        sel_byte1 = `OR1200_M2R_BYTE1;  // take byte 1
161
        endcase
162
end
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164
//
165
// Byte select 2
166
//
167
always @(addr or lsu_op) begin
168
        casex({lsu_op[2:0], addr})       // synopsys parallel_case
169
                {3'b010, 2'bxx},                        // lbz
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                {3'b100, 2'bxx}:                        // lhz
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                        sel_byte2 = `OR1200_M2R_ZERO;   // zero extend
172
                {3'b011, 2'b00},                        // lbs 0
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                {3'b101, 2'b00}:                        // lhs 0
174
                        sel_byte2 = `OR1200_M2R_EXTB3;  // sign extend from byte 3
175
                {3'b011, 2'b01}:                        // lbs 1
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                        sel_byte2 = `OR1200_M2R_EXTB2;  // sign extend from byte 2
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                {3'b011, 2'b10},                        // lbs 2
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                {3'b101, 2'b10}:                        // lhs 0
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                        sel_byte2 = `OR1200_M2R_EXTB1;  // sign extend from byte 1
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                {3'b011, 2'b11}:                        // lbs 3
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                        sel_byte2 = `OR1200_M2R_EXTB0;  // sign extend from byte 0
182
                default:                                // all other cases
183
                        sel_byte2 = `OR1200_M2R_BYTE2;  // take byte 2
184
        endcase
185
end
186
 
187
//
188
// Byte select 3
189
//
190
always @(addr or lsu_op) begin
191
        casex({lsu_op[2:0], addr}) // synopsys parallel_case
192
                {3'b010, 2'bxx},                        // lbz
193
                {3'b100, 2'bxx}:                        // lhz
194
                        sel_byte3 = `OR1200_M2R_ZERO;   // zero extend
195
                {3'b011, 2'b00},                        // lbs 0
196
                {3'b101, 2'b00}:                        // lhs 0
197
                        sel_byte3 = `OR1200_M2R_EXTB3;  // sign extend from byte 3
198
                {3'b011, 2'b01}:                        // lbs 1
199
                        sel_byte3 = `OR1200_M2R_EXTB2;  // sign extend from byte 2
200
                {3'b011, 2'b10},                        // lbs 2
201
                {3'b101, 2'b10}:                        // lhs 0
202
                        sel_byte3 = `OR1200_M2R_EXTB1;  // sign extend from byte 1
203
                {3'b011, 2'b11}:                        // lbs 3
204
                        sel_byte3 = `OR1200_M2R_EXTB0;  // sign extend from byte 0
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                default:                                // all other cases
206
                        sel_byte3 = `OR1200_M2R_BYTE3;  // take byte 3
207
        endcase
208
end
209
 
210
//
211
// Byte 0
212
//
213
always @(sel_byte0 or memdata) begin
214
`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
215
`ifdef OR1200_CASE_DEFAULT
216
        case(sel_byte0) // synopsys parallel_case infer_mux
217
`else
218
        case(sel_byte0) // synopsys full_case parallel_case infer_mux
219
`endif
220
`else
221
`ifdef OR1200_CASE_DEFAULT
222
        case(sel_byte0) // synopsys parallel_case
223
`else
224
        case(sel_byte0) // synopsys full_case parallel_case
225
`endif
226
`endif
227
                `OR1200_M2R_BYTE0: begin
228
                                regdata_ll = memdata[7:0];
229
                        end
230
                `OR1200_M2R_BYTE1: begin
231
                                regdata_ll = memdata[15:8];
232
                        end
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                `OR1200_M2R_BYTE2: begin
234
                                regdata_ll = memdata[23:16];
235
                        end
236
`ifdef OR1200_CASE_DEFAULT
237
                default: begin
238
`else
239
                `OR1200_M2R_BYTE3: begin
240
`endif
241
                                regdata_ll = memdata[31:24];
242
                        end
243
        endcase
244
end
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246
//
247
// Byte 1
248
//
249
always @(sel_byte1 or memdata) begin
250
`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
251
`ifdef OR1200_CASE_DEFAULT
252
        case(sel_byte1) // synopsys parallel_case infer_mux
253
`else
254
        case(sel_byte1) // synopsys full_case parallel_case infer_mux
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`endif
256
`else
257
`ifdef OR1200_CASE_DEFAULT
258
        case(sel_byte1) // synopsys parallel_case
259
`else
260
        case(sel_byte1) // synopsys full_case parallel_case
261
`endif
262
`endif
263
                `OR1200_M2R_ZERO: begin
264
                                regdata_lh = 8'h00;
265
                        end
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                `OR1200_M2R_BYTE1: begin
267
                                regdata_lh = memdata[15:8];
268
                        end
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                `OR1200_M2R_BYTE3: begin
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                                regdata_lh = memdata[31:24];
271
                        end
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                `OR1200_M2R_EXTB0: begin
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                                regdata_lh = {8{memdata[7]}};
274
                        end
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                `OR1200_M2R_EXTB1: begin
276
                                regdata_lh = {8{memdata[15]}};
277
                        end
278
                `OR1200_M2R_EXTB2: begin
279
                                regdata_lh = {8{memdata[23]}};
280
                        end
281
`ifdef OR1200_CASE_DEFAULT
282
                default: begin
283
`else
284
                `OR1200_M2R_EXTB3: begin
285
`endif
286
                                regdata_lh = {8{memdata[31]}};
287
                        end
288
        endcase
289
end
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291
//
292
// Byte 2
293
//
294
always @(sel_byte2 or memdata) begin
295
`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
296
`ifdef OR1200_CASE_DEFAULT
297
        case(sel_byte2) // synopsys parallel_case infer_mux
298
`else
299
        case(sel_byte2) // synopsys full_case parallel_case infer_mux
300
`endif
301
`else
302
`ifdef OR1200_CASE_DEFAULT
303
        case(sel_byte2) // synopsys parallel_case
304
`else
305
        case(sel_byte2) // synopsys full_case parallel_case
306
`endif
307
`endif
308
                `OR1200_M2R_ZERO: begin
309
                                regdata_hl = 8'h00;
310
                        end
311
                `OR1200_M2R_BYTE2: begin
312
                                regdata_hl = memdata[23:16];
313
                        end
314
                `OR1200_M2R_EXTB0: begin
315
                                regdata_hl = {8{memdata[7]}};
316
                        end
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                `OR1200_M2R_EXTB1: begin
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                                regdata_hl = {8{memdata[15]}};
319
                        end
320
                `OR1200_M2R_EXTB2: begin
321
                                regdata_hl = {8{memdata[23]}};
322
                        end
323
`ifdef OR1200_CASE_DEFAULT
324
                default: begin
325
`else
326
                `OR1200_M2R_EXTB3: begin
327
`endif
328
                                regdata_hl = {8{memdata[31]}};
329
                        end
330
        endcase
331
end
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333
//
334
// Byte 3
335
//
336
always @(sel_byte3 or memdata) begin
337
`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
338
`ifdef OR1200_CASE_DEFAULT
339
        case(sel_byte3) // synopsys parallel_case infer_mux
340
`else
341
        case(sel_byte3) // synopsys full_case parallel_case infer_mux
342
`endif
343
`else
344
`ifdef OR1200_CASE_DEFAULT
345
        case(sel_byte3) // synopsys parallel_case
346
`else
347
        case(sel_byte3) // synopsys full_case parallel_case
348
`endif
349
`endif
350
                `OR1200_M2R_ZERO: begin
351
                                regdata_hh = 8'h00;
352
                        end
353
                `OR1200_M2R_BYTE3: begin
354
                                regdata_hh = memdata[31:24];
355
                        end
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                `OR1200_M2R_EXTB0: begin
357
                                regdata_hh = {8{memdata[7]}};
358
                        end
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                `OR1200_M2R_EXTB1: begin
360
                                regdata_hh = {8{memdata[15]}};
361
                        end
362
                `OR1200_M2R_EXTB2: begin
363
                                regdata_hh = {8{memdata[23]}};
364
                        end
365
`ifdef OR1200_CASE_DEFAULT
366
                `OR1200_M2R_EXTB3: begin
367
`else
368
                `OR1200_M2R_EXTB3: begin
369
`endif
370
                                regdata_hh = {8{memdata[31]}};
371
                        end
372
        endcase
373
end
374
 
375
`else
376
 
377
//
378
// Straightforward implementation of mem2reg
379
//
380
 
381
reg     [width-1:0]              regdata;
382
reg     [width-1:0]              aligned;
383
 
384
//
385
// Alignment
386
//
387
always @(addr or memdata) begin
388
`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
389
        case(addr) // synopsys parallel_case infer_mux
390
`else
391
        case(addr) // synopsys parallel_case
392
`endif
393
                2'b00:
394
                        aligned = memdata;
395
                2'b01:
396
                        aligned = {memdata[23:0], 8'b0};
397
                2'b10:
398
                        aligned = {memdata[15:0], 16'b0};
399
                2'b11:
400
                        aligned = {memdata[7:0], 24'b0};
401
        endcase
402
end
403
 
404
//
405
// Bytes
406
//
407
always @(lsu_op or aligned) begin
408
`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
409
        case(lsu_op) // synopsys parallel_case infer_mux
410
`else
411
        case(lsu_op) // synopsys parallel_case
412
`endif
413
                `OR1200_LSUOP_LBZ: begin
414
                                regdata[7:0] = aligned[31:24];
415
                                regdata[31:8] = 24'b0;
416
                        end
417
                `OR1200_LSUOP_LBS: begin
418
                                regdata[7:0] = aligned[31:24];
419
                                regdata[31:8] = {24{aligned[31]}};
420
                        end
421
                `OR1200_LSUOP_LHZ: begin
422
                                regdata[15:0] = aligned[31:16];
423
                                regdata[31:16] = 16'b0;
424
                        end
425
                `OR1200_LSUOP_LHS: begin
426
                                regdata[15:0] = aligned[31:16];
427
                                regdata[31:16] = {16{aligned[31]}};
428
                        end
429
                default:
430
                                regdata = aligned;
431
        endcase
432
end
433
 
434
`endif
435
 
436
endmodule

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