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[/] [claw/] [trunk/] [or1200_cpu/] [or1200_operandmuxes.v] - Blame information for rev 4

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's register file read operands mux                    ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  Mux for two register file read operands.                    ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////  Modified by:                                                ////
////      - Balaji V. Iyer, bviyer@ncsu.edu                       ////
////  Advisor:                                                    ////
////      - Dr. Tom Conte                                         ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2  2002/03/29 15:16:56  lampret
// Some of the warnings fixed.
//
// Revision 1.1  2002/01/03 08:16:15  lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.9  2001/11/12 01:45:40  lampret
// Moved flag bit into SR. Changed RF enable from constant enable to dynamic enable for read ports.
//
// Revision 1.8  2001/10/21 17:57:16  lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.7  2001/10/14 13:12:09  lampret
// MP3 version.
//
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
// no message
//
// Revision 1.2  2001/08/09 13:39:33  lampret
// Major clean-up.
//
// Revision 1.1  2001/07/20 00:46:05  lampret
// Development version of RTL. Libraries are missing.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
module or1200_operandmuxes(
        // Clock and reset
        clk, rst,
 
        // Internal i/f
        id_freeze, ex_freeze, rf_dataa, rf_datab, ex_forw, wb_forw,
        rf_dataa2, rf_datab2, ex_forw2, wb_forw2,
        simm, sel_a, sel_b, operand_a, operand_b, muxed_b,
        simm2, sel_a2, sel_b2, operand_a2, operand_b2, muxed_b2,
        thread_in, thread_out
);
 
parameter width = 32;// `OR1200_OPERAND_WIDTH;
 
//
// I/O
//
input                           clk;
input                           rst;
input                           id_freeze;
input                           ex_freeze;
input   [width-1:0]              rf_dataa;
input   [width-1:0]              rf_datab;
input   [width-1:0]              rf_dataa2;
input   [width-1:0]              rf_datab2;
input   [width-1:0]              ex_forw;
input   [width-1:0]              wb_forw;
input   [width-1:0]              ex_forw2; // bviyer
input   [width-1:0]              wb_forw2; // bviyer
input   [width-1:0]              simm;
input   [width-1:0]              simm2;    // bviyer
input   [`OR1200_SEL_WIDTH-1:0]  sel_a;
input   [`OR1200_SEL_WIDTH-1:0]  sel_b;
input   [`OR1200_SEL_WIDTH-1:0]  sel_a2;  // bviyer
input   [`OR1200_SEL_WIDTH-1:0]  sel_b2;  // bviyer
output  [width-1:0]              operand_a;
output  [width-1:0]              operand_b;
output  [width-1:0]              operand_a2; // bviyer
output  [width-1:0]              operand_b2; // bviyer
output  [width-1:0]              muxed_b;
output  [width-1:0]              muxed_b2;  // bviyer
input   [2:0]                    thread_in; // bviyer
output  [2:0]                    thread_out; // bviyer
 
//
// Internal wires and regs
//
reg     [width-1:0]              operand_a;
reg     [width-1:0]              operand_b;
reg     [width-1:0]              operand_a2;
reg     [width-1:0]              operand_b2;
reg     [width-1:0]              muxed_a;
reg     [width-1:0]              muxed_b;
reg     [width-1:0]              muxed_a2;
reg     [width-1:0]              muxed_b2;
reg                             saved_a;
reg                             saved_b;
reg                             saved_a2;
reg                             saved_b2;
 
//
// Operand A register
//
always @(posedge clk or posedge rst) begin
        if (rst) begin
                operand_a <=  32'd0;
                saved_a <=  1'b0;
        end else if (!ex_freeze && id_freeze && !saved_a) begin
                operand_a <=  muxed_a;
                saved_a <=  1'b1;
        end else if (!ex_freeze && !saved_a) begin
                operand_a <=  muxed_a;
        end else if (!ex_freeze && !id_freeze)
                saved_a <=  1'b0;
end
 
//
// Operand A register
//
// bviyer: this way we are making a room for anther set of input to make it two way.
 
always @(posedge clk or posedge rst) begin
        if (rst) begin
                operand_a2 <=  32'd0;
                saved_a2 <=  1'b0;
        end else if (!ex_freeze && id_freeze && !saved_a2) begin
                operand_a2 <=  muxed_a2;
                saved_a2 <=  1'b1;
        end else if (!ex_freeze && !saved_a2) begin
                operand_a2 <=  muxed_a2;
        end else if (!ex_freeze && !id_freeze)
                saved_a2 <=  1'b0;
end
 
 
//
// Operand B register
//
always @(posedge clk or posedge rst) begin
        if (rst) begin
                operand_b <=  32'd0;
                saved_b <=  1'b0;
        end else if (!ex_freeze && id_freeze && !saved_b) begin
                operand_b <=  muxed_b;
                saved_b <=  1'b1;
        end else if (!ex_freeze && !saved_b) begin
                operand_b <=  muxed_b;
        end else if (!ex_freeze && !id_freeze)
                saved_b <=  1'b0;
end
//
// Operand B register
//
// bviyer: same as waht we did for operand A
always @(posedge clk or posedge rst) begin
        if (rst) begin
                operand_b2 <=  32'd0;
                saved_b2 <=  1'b0;
        end else if (!ex_freeze && id_freeze && !saved_b2) begin
                operand_b2 <=  muxed_b2;
                saved_b2 <=  1'b1;
        end else if (!ex_freeze && !saved_b2) begin
                operand_b2 <=  muxed_b2;
        end else if (!ex_freeze && !id_freeze)
                saved_b2 <=  1'b0;
end
 
//
// Forwarding logic for operand A register
//
always @(ex_forw or wb_forw or rf_dataa or sel_a) begin
`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
        casex (sel_a)   // synopsys parallel_case infer_mux
`else
        casex (sel_a)   // synopsys parallel_case
`endif
                `OR1200_SEL_EX_FORW:
                        muxed_a = ex_forw;
                `OR1200_SEL_WB_FORW:
                        muxed_a = wb_forw;
                default:
                        muxed_a = rf_dataa;
        endcase
end
 
 
//
// Forwarding logic for operand A register
//
// bviyer: forwarding logic for the 2nd a register.
always @(ex_forw2 or wb_forw2 or rf_dataa2 or sel_a2) begin
`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
        casex (sel_a2)  // synopsys parallel_case infer_mux
`else
        casex (sel_a2)  // synopsys parallel_case
`endif
                `OR1200_SEL_EX_FORW:
                        muxed_a2 = ex_forw2;
                `OR1200_SEL_WB_FORW:
                        muxed_a2 = wb_forw2;
                default:
                        muxed_a2 = rf_dataa2;
        endcase
end
 
 
 
 
 
//
// Forwarding logic for operand B register
//
always @(simm or ex_forw or wb_forw or rf_datab or sel_b) begin
`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
        casex (sel_b)   // synopsys parallel_case infer_mux
`else
        casex (sel_b)   // synopsys parallel_case
`endif
                `OR1200_SEL_IMM:
                        muxed_b = simm;
                `OR1200_SEL_EX_FORW:
                        muxed_b = ex_forw;
                `OR1200_SEL_WB_FORW:
                        muxed_b = wb_forw;
                default:
                        muxed_b = rf_datab;
        endcase
end
 
//
// Forwarding logic for operand B register
//
// bviyer: forwarding logic for the 2nd b register
 
always @(simm2 or ex_forw2 or wb_forw2 or rf_datab2 or sel_b2) begin
`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
        casex (sel_b2)  // synopsys parallel_case infer_mux
`else
        casex (sel_b2)  // synopsys parallel_case
`endif
                `OR1200_SEL_IMM:
                        muxed_b2 = simm2;
                `OR1200_SEL_EX_FORW:
                        muxed_b2 = ex_forw2;
                `OR1200_SEL_WB_FORW:
                        muxed_b2 = wb_forw2;
                default:
                        muxed_b2 = rf_datab2;
        endcase
end
 
 
assign thread_out = thread_in;
 
endmodule

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[/] [claw/] [trunk/] [or1200_cpu/] [or1200_operandmuxes.v] - Blame information for rev 4

Line No.	Rev	Author	Line
1	2	conte	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's register file read operands mux ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Mux for two register file read operands. ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - make it smaller and faster ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// Modified by: ////`
17			`//// - Balaji V. Iyer, bviyer@ncsu.edu ////`
18			`//// Advisor: ////`
19			`//// - Dr. Tom Conte ////`
20			`//// ////`
21			`//////////////////////////////////////////////////////////////////////`
22			`//// ////`
23			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
24			`//// ////`
25			`//// This source file may be used and distributed without ////`
26			`//// restriction provided that this copyright statement is not ////`
27			`//// removed from the file and that any derivative work contains ////`
28			`//// the original copyright notice and the associated disclaimer. ////`
29			`//// ////`
30			`//// This source file is free software; you can redistribute it ////`
31			`//// and/or modify it under the terms of the GNU Lesser General ////`
32			`//// Public License as published by the Free Software Foundation; ////`
33			`//// either version 2.1 of the License, or (at your option) any ////`
34			`//// later version. ////`
35			`//// ////`
36			`//// This source is distributed in the hope that it will be ////`
37			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
38			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
39			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
40			`//// details. ////`
41			`//// ////`
42			`//// You should have received a copy of the GNU Lesser General ////`
43			`//// Public License along with this source; if not, download it ////`
44			`//// from http://www.opencores.org/lgpl.shtml ////`
45			`//// ////`
46			`//////////////////////////////////////////////////////////////////////`
47			`//`
48			`// CVS Revision History`
49			`//`
50			`// $Log: not supported by cvs2svn $`
51			`// Revision 1.2 2002/03/29 15:16:56 lampret`
52			`// Some of the warnings fixed.`
53			`//`
54			`// Revision 1.1 2002/01/03 08:16:15 lampret`
55			`// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.`
56			`//`
57			`// Revision 1.9 2001/11/12 01:45:40 lampret`
58			`// Moved flag bit into SR. Changed RF enable from constant enable to dynamic enable for read ports.`
59			`//`
60			`// Revision 1.8 2001/10/21 17:57:16 lampret`
61			`// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.`
62			`//`
63			`// Revision 1.7 2001/10/14 13:12:09 lampret`
64			`// MP3 version.`
65			`//`
66			`// Revision 1.1.1.1 2001/10/06 10:18:36 igorm`
67			`// no message`
68			`//`
69			`// Revision 1.2 2001/08/09 13:39:33 lampret`
70			`// Major clean-up.`
71			`//`
72			`// Revision 1.1 2001/07/20 00:46:05 lampret`
73			`// Development version of RTL. Libraries are missing.`
74			`//`
75			`//`
76
77			`// synopsys translate_off`
78			`include "timescale.v"
79			`// synopsys translate_on`
80			`include "or1200_defines.v"
81
82			`module or1200_operandmuxes(`
83			`// Clock and reset`
84			`clk, rst,`
85
86			`// Internal i/f`
87			`id_freeze, ex_freeze, rf_dataa, rf_datab, ex_forw, wb_forw,`
88			`rf_dataa2, rf_datab2, ex_forw2, wb_forw2,`
89			`simm, sel_a, sel_b, operand_a, operand_b, muxed_b,`
90			`simm2, sel_a2, sel_b2, operand_a2, operand_b2, muxed_b2,`
91			`thread_in, thread_out`
92			`);`
93
94			parameter width = 32;// `OR1200_OPERAND_WIDTH;
95
96			`//`
97			`// I/O`
98			`//`
99			`input clk;`
100			`input rst;`
101			`input id_freeze;`
102			`input ex_freeze;`
103			`input [width-1:0] rf_dataa;`
104			`input [width-1:0] rf_datab;`
105			`input [width-1:0] rf_dataa2;`
106			`input [width-1:0] rf_datab2;`
107			`input [width-1:0] ex_forw;`
108			`input [width-1:0] wb_forw;`
109			`input [width-1:0] ex_forw2; // bviyer`
110			`input [width-1:0] wb_forw2; // bviyer`
111			`input [width-1:0] simm;`
112			`input [width-1:0] simm2; // bviyer`
113			input [`OR1200_SEL_WIDTH-1:0] sel_a;
114			input [`OR1200_SEL_WIDTH-1:0] sel_b;
115			input [`OR1200_SEL_WIDTH-1:0] sel_a2; // bviyer
116			input [`OR1200_SEL_WIDTH-1:0] sel_b2; // bviyer
117			`output [width-1:0] operand_a;`
118			`output [width-1:0] operand_b;`
119			`output [width-1:0] operand_a2; // bviyer`
120			`output [width-1:0] operand_b2; // bviyer`
121			`output [width-1:0] muxed_b;`
122			`output [width-1:0] muxed_b2; // bviyer`
123			`input [2:0] thread_in; // bviyer`
124			`output [2:0] thread_out; // bviyer`
125
126			`//`
127			`// Internal wires and regs`
128			`//`
129			`reg [width-1:0] operand_a;`
130			`reg [width-1:0] operand_b;`
131			`reg [width-1:0] operand_a2;`
132			`reg [width-1:0] operand_b2;`
133			`reg [width-1:0] muxed_a;`
134			`reg [width-1:0] muxed_b;`
135			`reg [width-1:0] muxed_a2;`
136			`reg [width-1:0] muxed_b2;`
137			`reg saved_a;`
138			`reg saved_b;`
139			`reg saved_a2;`
140			`reg saved_b2;`
141
142			`//`
143			`// Operand A register`
144			`//`
145			`always @(posedge clk or posedge rst) begin`
146			`if (rst) begin`
147			`operand_a <= 32'd0;`
148			`saved_a <= 1'b0;`
149			`end else if (!ex_freeze && id_freeze && !saved_a) begin`
150			`operand_a <= muxed_a;`
151			`saved_a <= 1'b1;`
152			`end else if (!ex_freeze && !saved_a) begin`
153			`operand_a <= muxed_a;`
154			`end else if (!ex_freeze && !id_freeze)`
155			`saved_a <= 1'b0;`
156			`end`
157
158			`//`
159			`// Operand A register`
160			`//`
161			`// bviyer: this way we are making a room for anther set of input to make it two way.`
162
163			`always @(posedge clk or posedge rst) begin`
164			`if (rst) begin`
165			`operand_a2 <= 32'd0;`
166			`saved_a2 <= 1'b0;`
167			`end else if (!ex_freeze && id_freeze && !saved_a2) begin`
168			`operand_a2 <= muxed_a2;`
169			`saved_a2 <= 1'b1;`
170			`end else if (!ex_freeze && !saved_a2) begin`
171			`operand_a2 <= muxed_a2;`
172			`end else if (!ex_freeze && !id_freeze)`
173			`saved_a2 <= 1'b0;`
174			`end`
175
176
177			`//`
178			`// Operand B register`
179			`//`
180			`always @(posedge clk or posedge rst) begin`
181			`if (rst) begin`
182			`operand_b <= 32'd0;`
183			`saved_b <= 1'b0;`
184			`end else if (!ex_freeze && id_freeze && !saved_b) begin`
185			`operand_b <= muxed_b;`
186			`saved_b <= 1'b1;`
187			`end else if (!ex_freeze && !saved_b) begin`
188			`operand_b <= muxed_b;`
189			`end else if (!ex_freeze && !id_freeze)`
190			`saved_b <= 1'b0;`
191			`end`
192			`//`
193			`// Operand B register`
194			`//`
195			`// bviyer: same as waht we did for operand A`
196			`always @(posedge clk or posedge rst) begin`
197			`if (rst) begin`
198			`operand_b2 <= 32'd0;`
199			`saved_b2 <= 1'b0;`
200			`end else if (!ex_freeze && id_freeze && !saved_b2) begin`
201			`operand_b2 <= muxed_b2;`
202			`saved_b2 <= 1'b1;`
203			`end else if (!ex_freeze && !saved_b2) begin`
204			`operand_b2 <= muxed_b2;`
205			`end else if (!ex_freeze && !id_freeze)`
206			`saved_b2 <= 1'b0;`
207			`end`
208
209			`//`
210			`// Forwarding logic for operand A register`
211			`//`
212			`always @(ex_forw or wb_forw or rf_dataa or sel_a) begin`
213			`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
214			`casex (sel_a) // synopsys parallel_case infer_mux`
215			`else
216			`casex (sel_a) // synopsys parallel_case`
217			`endif
218			`OR1200_SEL_EX_FORW:
219			`muxed_a = ex_forw;`
220			`OR1200_SEL_WB_FORW:
221			`muxed_a = wb_forw;`
222			`default:`
223			`muxed_a = rf_dataa;`
224			`endcase`
225			`end`
226
227
228			`//`
229			`// Forwarding logic for operand A register`
230			`//`
231			`// bviyer: forwarding logic for the 2nd a register.`
232			`always @(ex_forw2 or wb_forw2 or rf_dataa2 or sel_a2) begin`
233			`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
234			`casex (sel_a2) // synopsys parallel_case infer_mux`
235			`else
236			`casex (sel_a2) // synopsys parallel_case`
237			`endif
238			`OR1200_SEL_EX_FORW:
239			`muxed_a2 = ex_forw2;`
240			`OR1200_SEL_WB_FORW:
241			`muxed_a2 = wb_forw2;`
242			`default:`
243			`muxed_a2 = rf_dataa2;`
244			`endcase`
245			`end`
246
247
248
249
250
251			`//`
252			`// Forwarding logic for operand B register`
253			`//`
254			`always @(simm or ex_forw or wb_forw or rf_datab or sel_b) begin`
255			`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
256			`casex (sel_b) // synopsys parallel_case infer_mux`
257			`else
258			`casex (sel_b) // synopsys parallel_case`
259			`endif
260			`OR1200_SEL_IMM:
261			`muxed_b = simm;`
262			`OR1200_SEL_EX_FORW:
263			`muxed_b = ex_forw;`
264			`OR1200_SEL_WB_FORW:
265			`muxed_b = wb_forw;`
266			`default:`
267			`muxed_b = rf_datab;`
268			`endcase`
269			`end`
270
271			`//`
272			`// Forwarding logic for operand B register`
273			`//`
274			`// bviyer: forwarding logic for the 2nd b register`
275
276			`always @(simm2 or ex_forw2 or wb_forw2 or rf_datab2 or sel_b2) begin`
277			`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
278			`casex (sel_b2) // synopsys parallel_case infer_mux`
279			`else
280			`casex (sel_b2) // synopsys parallel_case`
281			`endif
282			`OR1200_SEL_IMM:
283			`muxed_b2 = simm2;`
284			`OR1200_SEL_EX_FORW:
285			`muxed_b2 = ex_forw2;`
286			`OR1200_SEL_WB_FORW:
287			`muxed_b2 = wb_forw2;`
288			`default:`
289			`muxed_b2 = rf_datab2;`
290			`endcase`
291			`end`
292
293
294			`assign thread_out = thread_in;`
295
296			`endmodule`