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[/] [claw/] [trunk/] [or1200_cpu/] [or1200_pic.v] - Blame information for rev 4

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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  OR1200's Programmable Interrupt Controller                  ////
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////                                                              ////
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////  This file is part of the OpenRISC 1200 project              ////
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////  http://www.opencores.org/cores/or1k/                        ////
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////                                                              ////
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////  Description                                                 ////
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////  PIC according to OR1K architectural specification.          ////
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////                                                              ////
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////  To Do:                                                      ////
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////   None                                                       ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Damjan Lampret, lampret@opencores.org                 ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
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// Revision 1.3  2002/03/29 15:16:56  lampret
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// Some of the warnings fixed.
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//
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// Revision 1.2  2002/01/18 07:56:00  lampret
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// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.
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//
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// Revision 1.1  2002/01/03 08:16:15  lampret
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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//
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// Revision 1.8  2001/10/21 17:57:16  lampret
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// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
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//
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// Revision 1.7  2001/10/14 13:12:10  lampret
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// MP3 version.
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//
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// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
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// no message
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//
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// Revision 1.2  2001/08/09 13:39:33  lampret
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// Major clean-up.
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//
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// Revision 1.1  2001/07/20 00:46:21  lampret
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// Development version of RTL. Libraries are missing.
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//
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//
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// synopsys translate_off
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`include "timescale.v"
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// synopsys translate_on
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`include "or1200_defines.v"
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module or1200_pic(
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        // RISC Internal Interface
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        clk, rst, spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o,
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        pic_wakeup, int,
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        // PIC Interface
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        pic_int
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);
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//
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// RISC Internal Interface
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//
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input           clk;            // Clock
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input           rst;            // Reset
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input           spr_cs;         // SPR CS
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input           spr_write;      // SPR Write
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input   [31:0]   spr_addr;       // SPR Address
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input   [31:0]   spr_dat_i;      // SPR Write Data
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output  [31:0]   spr_dat_o;      // SPR Read Data
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output          pic_wakeup;     // Wakeup to the PM
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output          int;            // interrupt
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                                // exception request
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//
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// PIC Interface
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//
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input   [`OR1200_PIC_INTS-1:0]   pic_int;// Interrupt inputs
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`ifdef OR1200_PIC_IMPLEMENTED
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//
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// PIC Mask Register bits (or no register)
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//
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`ifdef OR1200_PIC_PICMR
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reg     [`OR1200_PIC_INTS-1:2]  picmr;  // PICMR bits
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`else
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wire    [`OR1200_PIC_INTS-1:2]  picmr;  // No PICMR register
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`endif
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//
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// PIC Status Register bits (or no register)
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//
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`ifdef OR1200_PIC_PICSR
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reg     [`OR1200_PIC_INTS-1:0]   picsr;  // PICSR bits
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`else
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wire    [`OR1200_PIC_INTS-1:0]   picsr;  // No PICSR register
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`endif
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//
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// Internal wires & regs
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//
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wire            picmr_sel;      // PICMR select
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wire            picsr_sel;      // PICSR select
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wire    [`OR1200_PIC_INTS-1:0] um_ints;// Unmasked interrupts
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reg     [31:0]   spr_dat_o;      // SPR data out
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//
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// PIC registers address decoder
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//
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assign picmr_sel = (spr_cs && (spr_addr[`OR1200_PICOFS_BITS] == `OR1200_PIC_OFS_PICMR)) ? 1'b1 : 1'b0;
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assign picsr_sel = (spr_cs && (spr_addr[`OR1200_PICOFS_BITS] == `OR1200_PIC_OFS_PICSR)) ? 1'b1 : 1'b0;
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//
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// Write to PICMR
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//
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`ifdef OR1200_PIC_PICMR
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always @(posedge clk or posedge rst)
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        if (rst)
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                picmr <= {1'b1, {`OR1200_PIC_INTS-3{1'b0}}};
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        else if (picmr_sel && spr_write) begin
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                picmr <= #1 spr_dat_i[`OR1200_PIC_INTS-1:2];
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        end
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`else
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assign picmr = (`OR1200_PIC_INTS)'b1;
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`endif
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//
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// Write to PICSR, both CPU and external ints
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//
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`ifdef OR1200_PIC_PICSR
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always @(posedge clk or posedge rst)
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        if (rst)
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                picsr <= {`OR1200_PIC_INTS-2{1'b0}};
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        else if (picsr_sel && spr_write) begin
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                picsr <= #1 spr_dat_i[`OR1200_PIC_INTS-1:0] | um_ints;
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        end else
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                picsr <= #1 picsr | um_ints;
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`else
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assign picsr = pic_int;
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`endif
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//
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// Read PIC registers
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//
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always @(spr_addr or picmr or picsr)
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        case (spr_addr[`OR1200_PICOFS_BITS])    // synopsys parallel_case
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`ifdef OR1200_PIC_READREGS
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                `OR1200_PIC_OFS_PICMR: begin
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                                        spr_dat_o[`OR1200_PIC_INTS-1:0] = {picmr, 2'b0};
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`ifdef OR1200_PIC_UNUSED_ZERO
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                                        spr_dat_o[31:`OR1200_PIC_INTS] = {32-`OR1200_PIC_INTS{1'b0}};
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`endif
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                                end
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`endif
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                default: begin
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                                spr_dat_o[`OR1200_PIC_INTS-1:0] = picsr;
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`ifdef OR1200_PIC_UNUSED_ZERO
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                                spr_dat_o[31:`OR1200_PIC_INTS] = {32-`OR1200_PIC_INTS{1'b0}};
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`endif
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                        end
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        endcase
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//
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// Unmasked interrupts
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//
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assign um_ints = pic_int & {picmr, 2'b11};
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//
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// Generate int
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//
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assign int = |um_ints;
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//
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// Assert pic_wakeup when int is asserted
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//
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assign pic_wakeup = int;
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`else
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//
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// When PIC is not implemented, drive all outputs as would when PIC is disabled
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//
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assign int = pic_int[1] | pic_int[0];
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assign pic_wakeup= int;
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//
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// Read PIC registers
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//
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`ifdef OR1200_PIC_READREGS
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assign spr_dat_o[`OR1200_PIC_INTS-1:0] = `OR1200_PIC_INTS'b0;
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`ifdef OR1200_PIC_UNUSED_ZERO
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assign spr_dat_o[31:`OR1200_PIC_INTS] = 32-`OR1200_PIC_INTS'b0;
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`endif
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`endif
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`endif
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endmodule

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