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[/] [claw/] [trunk/] [or1200_cpu/] [or1200_pm.v] - Blame information for rev 4

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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  OR1200's Power Management                                   ////
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////                                                              ////
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////  This file is part of the OpenRISC 1200 project              ////
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////  http://www.opencores.org/cores/or1k/                        ////
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////                                                              ////
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////  Description                                                 ////
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////  PM according to OR1K architectural specification.           ////
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////                                                              ////
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////  To Do:                                                      ////
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////   - add support for dynamic clock gating                     ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Damjan Lampret, lampret@opencores.org                 ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
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// Revision 1.1  2002/01/03 08:16:15  lampret
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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//
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// Revision 1.8  2001/10/21 17:57:16  lampret
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// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
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//
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// Revision 1.7  2001/10/14 13:12:10  lampret
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// MP3 version.
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//
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// Revision 1.1.1.1  2001/10/06 10:18:35  igorm
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// no message
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//
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// Revision 1.2  2001/08/09 13:39:33  lampret
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// Major clean-up.
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//
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// Revision 1.1  2001/07/20 00:46:21  lampret
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// Development version of RTL. Libraries are missing.
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//
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//
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// synopsys translate_off
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`include "timescale.v"
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// synopsys translate_on
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`include "or1200_defines.v"
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module or1200_pm(
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        // RISC Internal Interface
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        clk, rst, pic_wakeup, spr_write, spr_addr, spr_dat_i, spr_dat_o,
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        // Power Management Interface
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        pm_clksd, pm_cpustall, pm_dc_gate, pm_ic_gate, pm_dmmu_gate,
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        pm_immu_gate, pm_tt_gate, pm_cpu_gate, pm_wakeup, pm_lvolt
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);
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//
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// RISC Internal Interface
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//
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input           clk;            // Clock
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input           rst;            // Reset
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input           pic_wakeup;     // Wakeup from the PIC
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input           spr_write;      // SPR Read/Write
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input   [31:0]   spr_addr;       // SPR Address
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input   [31:0]   spr_dat_i;      // SPR Write Data
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output  [31:0]   spr_dat_o;      // SPR Read Data
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//
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// Power Management Interface
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//
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input           pm_cpustall;    // Stall the CPU
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output  [3:0]    pm_clksd;       // Clock Slowdown factor
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output          pm_dc_gate;     // Gate DCache clock
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output          pm_ic_gate;     // Gate ICache clock
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output          pm_dmmu_gate;   // Gate DMMU clock
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output          pm_immu_gate;   // Gate IMMU clock
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output          pm_tt_gate;     // Gate Tick Timer clock
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output          pm_cpu_gate;    // Gate main RISC/CPU clock
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output          pm_wakeup;      // Activate (de-gate) all clocks
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output          pm_lvolt;       // Lower operating voltage
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`ifdef OR1200_PM_IMPLEMENTED
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//
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// Power Management Register bits
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//
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reg     [3:0]    sdf;    // Slow-down factor
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reg             dme;    // Doze Mode Enable
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reg             sme;    // Sleep Mode Enable
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reg             dcge;   // Dynamic Clock Gating Enable
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//
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// Internal wires
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//
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wire            pmr_sel; // PMR select
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//
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// PMR address decoder (partial decoder)
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//
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`ifdef OR1200_PM_PARTIAL_DECODING
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assign pmr_sel = (spr_addr[`OR1200_SPR_GROUP_BITS] == `OR1200_SPRGRP_PM) ? 1'b1 : 1'b0;
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`else
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assign pmr_sel = ((spr_addr[`OR1200_SPR_GROUP_BITS] == `OR1200_SPRGRP_PM) &&
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                  (spr_addr[`OR1200_SPR_OFS_BITS] == `OR1200_PM_OFS_PMR)) ? 1'b1 : 1'b0;
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`endif
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//
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// Write to PMR and also PMR[DME]/PMR[SME] reset when
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// pic_wakeup is asserted
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//
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always @(posedge clk or posedge rst)
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        if (rst)
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                {dcge, sme, dme, sdf} <= 7'b0;
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        else if (pmr_sel && spr_write) begin
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                sdf <= #1 spr_dat_i[`OR1200_PM_PMR_SDF];
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                dme <= #1 spr_dat_i[`OR1200_PM_PMR_DME];
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                sme <= #1 spr_dat_i[`OR1200_PM_PMR_SME];
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                dcge <= #1 spr_dat_i[`OR1200_PM_PMR_DCGE];
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        end
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        else if (pic_wakeup) begin
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                dme <= #1 1'b0;
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                sme <= #1 1'b0;
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        end
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//
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// Read PMR
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//
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`ifdef OR1200_PM_READREGS
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assign spr_dat_o[`OR1200_PM_PMR_SDF] = sdf;
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assign spr_dat_o[`OR1200_PM_PMR_DME] = dme;
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assign spr_dat_o[`OR1200_PM_PMR_SME] = sme;
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assign spr_dat_o[`OR1200_PM_PMR_DCGE] = dcge;
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`ifdef OR1200_PM_UNUSED_ZERO
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assign spr_dat_o[`OR1200_PM_PMR_UNUSED] = 25'b0;
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`endif
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`endif
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//
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// Generate pm_clksd
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//
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assign pm_clksd = sdf;
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//
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// Statically generate all clock gate outputs
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// TODO: add dynamic clock gating feature
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//
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assign pm_cpu_gate = (dme | sme) & ~pic_wakeup;
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assign pm_dc_gate = pm_cpu_gate;
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assign pm_ic_gate = pm_cpu_gate;
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assign pm_dmmu_gate = pm_cpu_gate;
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assign pm_immu_gate = pm_cpu_gate;
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assign pm_tt_gate = sme & ~pic_wakeup;
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//
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// Assert pm_wakeup when pic_wakeup is asserted
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//
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assign pm_wakeup = pic_wakeup;
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//
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// Assert pm_lvolt when pm_cpu_gate or pm_cpustall are asserted
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//
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assign pm_lvolt = pm_cpu_gate | pm_cpustall;
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`else
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//
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// When PM is not implemented, drive all outputs as would when PM is disabled
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//
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assign pm_clksd = 4'b0;
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assign pm_cpu_gate = 1'b0;
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assign pm_dc_gate = 1'b0;
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assign pm_ic_gate = 1'b0;
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assign pm_dmmu_gate = 1'b0;
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assign pm_immu_gate = 1'b0;
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assign pm_tt_gate = 1'b0;
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assign pm_wakeup = 1'b1;
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assign pm_lvolt = 1'b0;
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//
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// Read PMR
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//
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`ifdef OR1200_PM_READREGS
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assign spr_dat_o[`OR1200_PM_PMR_SDF] = 4'b0;
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assign spr_dat_o[`OR1200_PM_PMR_DME] = 1'b0;
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assign spr_dat_o[`OR1200_PM_PMR_SME] = 1'b0;
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assign spr_dat_o[`OR1200_PM_PMR_DCGE] = 1'b0;
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`ifdef OR1200_PM_UNUSED_ZERO
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assign spr_dat_o[`OR1200_PM_PMR_UNUSED] = 25'b0;
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`endif
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`endif
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`endif
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endmodule

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