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[/] [claw/] [trunk/] [or1200_cpu/] [or1200_rf_top.v] - Blame information for rev 4

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1 2 conte
//////////////////////////////////////////////////////////////////////
2
////  OR1200's correct register file chooser                      ////
3
////                                                              ////
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////                                                              ////
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////  Description                                                 ////
6
////   Chooses the appropriate register to write and read         ////
7
////                                                              ////
8
////  Written by:                                                 ////
9
////      - Balaji V. Iyer, bviyer@ncsu.edu                       ////
10
////  Advisor:                                                    ////
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////      - Dr. Tom Conte                                         ////
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////                                                              ////
13
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2004 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
23
//// and/or modify it under the terms of the GNU Lesser General   ////
24
//// Public License as published by the Free Software Foundation; ////
25
//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
30
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
31
//// PURPOSE.  See the GNU Lesser General Public License for more ////
32
//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
35
//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
39
 
40
// synopsys translate_off
41
`include "timescale.v"
42
// synopsys translate_on
43
`include "or1200_defines.v"
44
 
45
module or1200_rf_top(
46
        // Clock and reset
47
        clk, rst,
48
 
49
        // Write i/f
50
        supv, wb_freeze, addrw, dataw, addrw2, dataw2, we, we2, flushpipe,
51
 
52
        // Read i/f
53
        id_freeze, addra, addrb, dataa, datab, rda, rdb,
54
                   addra2,addrb2, dataa2, datab2, rda2, rdb2,
55
 
56
        // Debug
57
        spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o,
58
        current_thread_read, current_thread_read_out,
59
        current_thread_write
60
);
61
 
62
parameter dw = 32; //`OR1200_OPERAND_WIDTH;
63
parameter aw = 5; // `OR1200_REGFILE_ADDR_WIDTH;
64
 
65
//
66
// I/O
67
//
68
 
69
//
70
// Clock and reset
71
//
72
input                           clk;
73
input                           rst;
74
 
75
//
76
// Write i/f
77
//
78
input                           supv;
79
input                           wb_freeze;
80
input   [aw-1:0]         addrw;
81
input   [dw-1:0]         dataw;
82
input                           we;
83
input                           flushpipe;
84
 
85
 
86
//bviyer: this is used to hold the thread
87
 
88
input [2:0]              current_thread_read;
89
output [2:0]             current_thread_read_out;
90
reg [2:0]                current_thread_read_out;
91
input [2:0]              current_thread_write;
92
 
93
// bviyer: replicated the write port to two. One problem here we can face is that
94
// if two insturctions write the same register then we will have some biggie
95
// problems...but this is something that the compiler should take care of it. 
96
input [aw-1:0]                   addrw2;
97
input [dw-1:0]                   dataw2;
98
input                           we2;
99
//
100
// Read i/f
101
//
102
input                           id_freeze;
103
input   [aw-1:0]         addra;
104
input   [aw-1:0]         addrb;
105
output  [dw-1:0]         dataa;
106
reg     [dw-1:0]         dataa;
107
output  [dw-1:0]         datab;
108
reg     [dw-1:0]         datab;
109
input                           rda;
110
input                           rdb;
111
 
112
// bviyer: replicated the address and output ports to hold two values to the register file.
113
 
114
input [aw-1:0]                   addra2;
115
input [aw-1:0]                   addrb2;
116
output [dw-1:0]                  dataa2;
117
reg    [dw-1:0]                  dataa2;
118
output [dw-1:0]                  datab2;
119
reg    [dw-1:0]                  datab2;
120
input                           rda2;
121
input                           rdb2;
122
 
123
 
124
 
125
//
126
// SPR access for debugging purposes
127
//
128
input                           spr_cs;
129
input                           spr_write;
130
input   [31:0]                   spr_addr;
131
input   [31:0]                   spr_dat_i;
132
output  [31:0]                   spr_dat_o;
133
reg     [31:0]                   spr_dat_o;
134
 
135
//
136
// Internal wires and regs
137
//
138
 
139
wire[31:0] spr_dat_o_1;
140
wire[31:0] spr_dat_o_2;
141
wire[31:0] spr_dat_o_3;
142
wire[31:0] spr_dat_o_4;
143
wire[31:0] spr_dat_o_5;
144
wire[31:0] spr_dat_o_6;
145
wire[31:0] spr_dat_o_7;
146
wire[31:0] spr_dat_o_8;
147
 
148
 
149
// to hold different register A data of slot 1 
150
wire[31:0] dataa_1;
151
wire[31:0] dataa_2;
152
wire[31:0] dataa_3;
153
wire[31:0] dataa_4;
154
wire[31:0] dataa_5;
155
wire[31:0] dataa_6;
156
wire[31:0] dataa_7;
157
wire[31:0] dataa_8;
158
 
159
// to hold different register A data of slot 2
160
wire[31:0] dataa2_1;
161
wire[31:0] dataa2_2;
162
wire[31:0] dataa2_3;
163
wire[31:0] dataa2_4;
164
wire[31:0] dataa2_5;
165
wire[31:0] dataa2_6;
166
wire[31:0] dataa2_7;
167
wire[31:0] dataa2_8;
168
 
169
// to hold different register B data of slot 1
170
wire[31:0] datab_1;
171
wire[31:0] datab_2;
172
wire[31:0] datab_3;
173
wire[31:0] datab_4;
174
wire[31:0] datab_5;
175
wire[31:0] datab_6;
176
wire[31:0] datab_7;
177
wire[31:0] datab_8;
178
 
179
 
180
// to hold different register B data of slot 1
181
wire[31:0] datab2_1;
182
wire[31:0] datab2_2;
183
wire[31:0] datab2_3;
184
wire[31:0] datab2_4;
185
wire[31:0] datab2_5;
186
wire[31:0] datab2_6;
187
wire[31:0] datab2_7;
188
wire[31:0] datab2_8;
189
 
190
//differnt write enables to make sure we are not writing to every register
191
// just the ones we want.
192
 
193
wire we_1;
194
wire we_2;
195
wire we_3;
196
wire we_4;
197
wire we_5;
198
wire we_6;
199
wire we_7;
200
wire we_8;
201
 
202
// same for the write port two
203
 
204
wire we2_1;
205
wire we2_2;
206
wire we2_3;
207
wire we2_4;
208
wire we2_5;
209
wire we2_6;
210
wire we2_7;
211
wire we2_8;
212
 
213
 
214
// assigning the correct write enable
215
assign we_1 = we & (!current_thread_write[0] & !current_thread_write[1]
216
        & !current_thread_write[2]);
217
assign we_2 = we & (current_thread_write[0]  & !current_thread_write[1] &
218
        !current_thread_write[2]);
219
assign we_3 = we & (!current_thread_write[0] &  current_thread_write[1] &
220
        !current_thread_write[2]);
221
assign we_4 = we & (current_thread_write[0]  &  current_thread_write[1] &
222
        !current_thread_write[2]);
223
assign we_5 = we & (!current_thread_write[0] & !current_thread_write[1] &
224
        current_thread_write[2]);
225
assign we_6 = we & (current_thread_write[0]  & !current_thread_write[1] &
226
        current_thread_write[2]);
227
assign we_7 = we & (!current_thread_write[0] &  current_thread_write[1] &
228
        current_thread_write[2]);
229
assign we_8 = we & (current_thread_write[0]  &  current_thread_write[1] &
230
        current_thread_write[2]);
231
 
232
assign we2_1 = we2 & (!current_thread_write[0] & !current_thread_write[1]
233
        & !current_thread_write[2]);
234
assign we2_2 = we2 & (current_thread_write[0]  & !current_thread_write[1] &
235
        !current_thread_write[2]);
236
assign we2_3 = we2 & (!current_thread_write[0] &  current_thread_write[1] &
237
        !current_thread_write[2]);
238
assign we2_4 = we2 & (current_thread_write[0]  &  current_thread_write[1] &
239
        !current_thread_write[2]);
240
assign we2_5 = we2 & (!current_thread_write[0] & !current_thread_write[1] &
241
        current_thread_write[2]);
242
assign we2_6 = we2 & (current_thread_write[0]  & !current_thread_write[1] &
243
        current_thread_write[2]);
244
assign we2_7 = we2 & (!current_thread_write[0] &  current_thread_write[1] &
245
        current_thread_write[2]);
246
assign we2_8 = we2 & (current_thread_write[0]  &  current_thread_write[1] &
247
        current_thread_write[2]);
248
 
249
or1200_rf or1200_rf1(.clk(clk), .rst(rst), .supv(supv), .wb_freeze(wb_freeze),
250
  .addrw(addrw), .dataw(dataw), .addrw2(addrw2), .dataw2(dataw2), .we(we_1),
251
  .we2(we2_1), .flushpipe (flushpipe), .id_freeze(id_freeze), .addra(addra),
252
  .addrb(addrb), .dataa(dataa_1), .datab(datab_1), .rda(rda), .rdb(rdb),
253
  .addra2(addra2), .addrb2(addrb2), .dataa2(dataa2_1),
254
  .datab2(datab2_1), .rda2(rda2), .rdb2(rdb2), .spr_cs(spr_cs),
255
  .spr_write(spr_write), .spr_addr(spr_addr), .spr_dat_i(spr_dat_i),
256
  .spr_dat_o(spr_dat_o_1));
257
 
258
or1200_rf or1200_rf2(.clk(clk), .rst(rst), .supv(supv), .wb_freeze(wb_freeze),
259
  .addrw(addrw), .dataw(dataw), .addrw2(addrw2), .dataw2(dataw2), .we(we_2),
260
  .we2(we2_2), .flushpipe (flushpipe), .id_freeze(id_freeze), .addra(addra),
261
  .addrb(addrb), .dataa(dataa_2), .datab(datab_2), .rda(rda), .rdb(rdb),
262
  .addra2(addra2), .addrb2(addrb2), .dataa2(dataa2_2),
263
  .datab2(datab2_2), .rda2(rda2), .rdb2(rdb2), .spr_cs(spr_cs),
264
  .spr_write(spr_write), .spr_addr(spr_addr), .spr_dat_i(spr_dat_i),
265
  .spr_dat_o(spr_dat_o_2));
266
 
267
or1200_rf or1200_rf3(.clk(clk), .rst(rst), .supv(supv), .wb_freeze(wb_freeze),
268
  .addrw(addrw), .dataw(dataw), .addrw2(addrw2), .dataw2(dataw2), .we(we_3),
269
  .we2(we2_3), .flushpipe (flushpipe), .id_freeze(id_freeze), .addra(addra),
270
  .addrb(addrb), .dataa(dataa_3), .datab(datab_3), .rda(rda), .rdb(rdb),
271
  .addra2(addra2), .addrb2(addrb2), .dataa2(dataa2_3),
272
  .datab2(datab2_3), .rda2(rda2), .rdb2(rdb2), .spr_cs(spr_cs),
273
  .spr_write(spr_write), .spr_addr(spr_addr), .spr_dat_i(spr_dat_i),
274
  .spr_dat_o(spr_dat_o_3));
275
 
276
or1200_rf or1200_rf4(.clk(clk), .rst(rst), .supv(supv), .wb_freeze(wb_freeze),
277
  .addrw(addrw), .dataw(dataw), .addrw2(addrw2), .dataw2(dataw2), .we(we_4),
278
  .we2(we2_4), .flushpipe (flushpipe), .id_freeze(id_freeze), .addra(addra),
279
  .addrb(addrb), .dataa(dataa_4), .datab(datab_4), .rda(rda), .rdb(rdb),
280
  .addra2(addra2), .addrb2(addrb2), .dataa2(dataa2_4),
281
  .datab2(datab2_4), .rda2(rda2), .rdb2(rdb2), .spr_cs(spr_cs),
282
  .spr_write(spr_write), .spr_addr(spr_addr), .spr_dat_i(spr_dat_i),
283
  .spr_dat_o(spr_dat_o_4));
284
 
285
or1200_rf or1200_rf5(.clk(clk), .rst(rst), .supv(supv), .wb_freeze(wb_freeze),
286
  .addrw(addrw), .dataw(dataw), .addrw2(addrw2), .dataw2(dataw2), .we(we_5),
287
  .we2(we2_5), .flushpipe (flushpipe), .id_freeze(id_freeze), .addra(addra),
288
  .addrb(addrb), .dataa(dataa_5), .datab(datab_5), .rda(rda), .rdb(rdb),
289
  .addra2(addra2), .addrb2(addrb2), .dataa2(dataa2_5),
290
  .datab2(datab2_5), .rda2(rda2), .rdb2(rdb2), .spr_cs(spr_cs),
291
  .spr_write(spr_write), .spr_addr(spr_addr), .spr_dat_i(spr_dat_i),
292
  .spr_dat_o(spr_dat_o_5));
293
 
294
or1200_rf or1200_rf6(.clk(clk), .rst(rst), .supv(supv), .wb_freeze(wb_freeze),
295
  .addrw(addrw), .dataw(dataw), .addrw2(addrw2), .dataw2(dataw2), .we(we_6),
296
  .we2(we2_6), .flushpipe (flushpipe), .id_freeze(id_freeze), .addra(addra),
297
  .addrb(addrb), .dataa(dataa_6), .datab(datab_6), .rda(rda), .rdb(rdb),
298
  .addra2(addra2), .addrb2(addrb2), .dataa2(dataa2_6),
299
  .datab2(datab2_6), .rda2(rda2), .rdb2(rdb2), .spr_cs(spr_cs),
300
  .spr_write(spr_write), .spr_addr(spr_addr), .spr_dat_i(spr_dat_i),
301
  .spr_dat_o(spr_dat_o_6));
302
 
303
or1200_rf or1200_rf7(.clk(clk), .rst(rst), .supv(supv), .wb_freeze(wb_freeze),
304
  .addrw(addrw), .dataw(dataw), .addrw2(addrw2), .dataw2(dataw2), .we(we_7),
305
  .we2(we2_7), .flushpipe (flushpipe), .id_freeze(id_freeze), .addra(addra),
306
  .addrb(addrb), .dataa(dataa_7), .datab(datab_7), .rda(rda), .rdb(rdb),
307
  .addra2(addra2), .addrb2(addrb2), .dataa2(dataa2_7),
308
  .datab2(datab2_7), .rda2(rda2), .rdb2(rdb2), .spr_cs(spr_cs),
309
  .spr_write(spr_write), .spr_addr(spr_addr), .spr_dat_i(spr_dat_i),
310
  .spr_dat_o(spr_dat_o_7));
311
 
312
or1200_rf or1200_rf8(.clk(clk), .rst(rst), .supv(supv), .wb_freeze(wb_freeze),
313
  .addrw(addrw), .dataw(dataw), .addrw2(addrw2), .dataw2(dataw2), .we(we_8),
314
  .we2(we2_8), .flushpipe (flushpipe), .id_freeze(id_freeze), .addra(addra),
315
  .addrb(addrb), .dataa(dataa_8), .datab(datab_8), .rda(rda), .rdb(rdb),
316
  .addra2(addra2), .addrb2(addrb2), .dataa2(dataa2_8),
317
  .datab2(datab2_8), .rda2(rda2), .rdb2(rdb2), .spr_cs(spr_cs),
318
  .spr_write(spr_write), .spr_addr(spr_addr), .spr_dat_i(spr_dat_i),
319
  .spr_dat_o(spr_dat_o_8));
320
 
321
always @ (datab_1 or datab_2 or datab_3 or datab_4 or
322
          datab_5 or datab_6 or datab_7 or datab_8 or
323
          dataa_1 or dataa_2 or dataa_3 or dataa_4 or
324
          dataa_5 or dataa_6 or dataa_7 or dataa_8 or
325
          datab2_1 or datab2_2 or datab2_3 or datab2_4 or
326
          datab2_5 or datab2_6 or datab2_7 or datab2_8 or
327
          dataa2_1 or dataa2_2 or dataa2_3 or dataa2_4 or
328
          dataa2_5 or dataa2_6 or dataa2_7 or dataa2_8 or
329
          spr_dat_o_1 or spr_dat_o_2 or spr_dat_o_3 or spr_dat_o_4 or
330
          spr_dat_o_5 or spr_dat_o_6 or spr_dat_o_7 or spr_dat_o_8 or
331
          current_thread_read)
332
begin
333
        // current_thread_read_out <= current_thread_read;
334
   case (current_thread_read)           // synopsys parallel_case
335
        3'd0: begin
336
                dataa  <= dataa_1;
337
                datab  <= datab_1;
338
                dataa2 <= dataa2_1;
339
                datab2 <= datab2_1;
340
                spr_dat_o <= spr_dat_o_1;
341
                current_thread_read_out <= 3'd0;
342
                end
343
        3'd1: begin
344
                dataa  <= dataa_2;
345
                datab  <= datab_2;
346
                dataa2 <= dataa2_2;
347
                datab2 <= datab2_2;
348
                spr_dat_o <= spr_dat_o_2;
349
                current_thread_read_out <= 3'd1;
350
                end
351
        3'd2: begin
352
                dataa  <= dataa_3;
353
                datab  <= datab_3;
354
                dataa2 <= dataa2_3;
355
                datab2 <= datab2_3;
356
                spr_dat_o <= spr_dat_o_3;
357
                current_thread_read_out <= 3'd2;
358
                end
359
        3'd3: begin
360
                dataa  <= dataa_4;
361
                datab  <= datab_4;
362
                dataa2 <= dataa2_4;
363
                datab2 <= datab2_4;
364
                spr_dat_o <= spr_dat_o_4;
365
                current_thread_read_out <= 3'd3;
366
                end
367
        3'd4: begin
368
                dataa  <= dataa_5;
369
                datab  <= datab_5;
370
                dataa2 <= dataa2_5;
371
                datab2 <= datab2_5;
372
                spr_dat_o <= spr_dat_o_5;
373
                current_thread_read_out <= 3'd4;
374
                end
375
        3'd5: begin
376
                dataa  <= dataa_6;
377
                datab  <= datab_6;
378
                dataa2 <= dataa2_6;
379
                datab2 <= datab2_6;
380
                spr_dat_o <= spr_dat_o_6;
381
                current_thread_read_out <= 3'd5;
382
                end
383
        3'd6: begin
384
                dataa  <= dataa_7;
385
                datab  <= datab_7;
386
                dataa2 <= dataa2_7;
387
                datab2 <= datab2_7;
388
                spr_dat_o <= spr_dat_o_7;
389
                current_thread_read_out <= 3'd6;
390
                end
391
        3'd7: begin
392
                dataa  <= dataa_8;
393
                datab  <= datab_8;
394
                dataa2 <= dataa2_8;
395
                datab2 <= datab2_8;
396
                spr_dat_o <= spr_dat_o_8;
397
                current_thread_read_out <= 3'd7;
398
                end
399
   endcase
400
end
401
endmodule

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