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[/] [claw/] [trunk/] [or1200_cpu/] [or1200_sb.v] - Blame information for rev 4

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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  OR1200's Store Buffer                                       ////
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////                                                              ////
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////  This file is part of the OpenRISC 1200 project              ////
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////  http://www.opencores.org/cores/or1k/                        ////
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////                                                              ////
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////  Description                                                 ////
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////  Implements store buffer.                                    ////
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////                                                              ////
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////  To Do:                                                      ////
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////   - byte combining                                           ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Damjan Lampret, lampret@opencores.org                 ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2002 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
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// Revision 1.2  2002/08/22 02:18:55  lampret
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// Store buffer has been tested and it works. BY default it is still disabled until uClinux confirms correct operation on FPGA board.
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//
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// Revision 1.1  2002/08/18 19:53:08  lampret
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// Added store buffer.
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//
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//
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// synopsys translate_off
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`include "timescale.v"
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// synopsys translate_on
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`include "or1200_defines.v"
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module or1200_sb(
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        // RISC clock, reset
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        clk, rst,
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        // Internal RISC bus (DC<->SB)
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        dcsb_dat_i, dcsb_adr_i, dcsb_cyc_i, dcsb_stb_i, dcsb_we_i, dcsb_sel_i, dcsb_cab_i,
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        dcsb_dat_o, dcsb_ack_o, dcsb_err_o,
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        // BIU bus
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        sbbiu_dat_o, sbbiu_adr_o, sbbiu_cyc_o, sbbiu_stb_o, sbbiu_we_o, sbbiu_sel_o, sbbiu_cab_o,
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        sbbiu_dat_i, sbbiu_ack_i, sbbiu_err_i
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);
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parameter dw = `OR1200_OPERAND_WIDTH;
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parameter aw = `OR1200_OPERAND_WIDTH;
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//
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// RISC clock, reset
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//
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input                   clk;            // RISC clock
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input                   rst;            // RISC reset
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//
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// Internal RISC bus (DC<->SB)
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//
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input   [dw-1:0] dcsb_dat_i;     // input data bus
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input   [aw-1:0] dcsb_adr_i;     // address bus
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input                   dcsb_cyc_i;     // WB cycle
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input                   dcsb_stb_i;     // WB strobe
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input                   dcsb_we_i;      // WB write enable
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input                   dcsb_cab_i;     // CAB input
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input   [3:0]            dcsb_sel_i;     // byte selects
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output  [dw-1:0] dcsb_dat_o;     // output data bus
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output                  dcsb_ack_o;     // ack output
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output                  dcsb_err_o;     // err output
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//
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// BIU bus
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//
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output  [dw-1:0] sbbiu_dat_o;    // output data bus
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output  [aw-1:0] sbbiu_adr_o;    // address bus
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output                  sbbiu_cyc_o;    // WB cycle
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output                  sbbiu_stb_o;    // WB strobe
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output                  sbbiu_we_o;     // WB write enable
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output                  sbbiu_cab_o;    // CAB input
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output  [3:0]            sbbiu_sel_o;    // byte selects
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input   [dw-1:0] sbbiu_dat_i;    // input data bus
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input                   sbbiu_ack_i;    // ack output
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input                   sbbiu_err_i;    // err output
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`ifdef OR1200_SB_IMPLEMENTED
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//
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// Internal wires and regs
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//
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wire    [4+dw+aw-1:0]    fifo_dat_i;     // FIFO data in
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wire    [4+dw+aw-1:0]    fifo_dat_o;     // FIFO data out
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wire                    fifo_wr;
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wire                    fifo_rd;
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wire                    fifo_full;
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wire                    fifo_empty;
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wire                    sel_sb;
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reg                     outstanding_store;
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reg                     fifo_wr_ack;
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//
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// FIFO data in/out
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//
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assign fifo_dat_i = {dcsb_sel_i, dcsb_dat_i, dcsb_adr_i};
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assign {sbbiu_sel_o, sbbiu_dat_o, sbbiu_adr_o} = sel_sb ? fifo_dat_o : {dcsb_sel_i, dcsb_dat_i, dcsb_adr_i};
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//
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// Control
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//
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assign fifo_wr = dcsb_cyc_i & dcsb_stb_i & dcsb_we_i & ~fifo_full & ~fifo_wr_ack;
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assign fifo_rd = ~outstanding_store;
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assign dcsb_dat_o = sbbiu_dat_i;
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assign dcsb_ack_o = sel_sb ? fifo_wr_ack : sbbiu_ack_i;
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assign dcsb_err_o = sel_sb ? 1'b0 : sbbiu_err_i;        // SB never returns error
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assign sbbiu_cyc_o = sel_sb ? outstanding_store : dcsb_cyc_i;
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assign sbbiu_stb_o = sel_sb ? outstanding_store : dcsb_stb_i;
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assign sbbiu_we_o = sel_sb ? 1'b1 : dcsb_we_i;
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assign sbbiu_cab_o = sel_sb ? 1'b0 : dcsb_cab_i;
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assign sel_sb = ~fifo_empty | (fifo_empty & outstanding_store); // | fifo_wr;
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//
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// Store buffer FIFO instantiation
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//
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or1200_sb_fifo or1200_sb_fifo (
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        .clk_i(clk),
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        .rst_i(rst),
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        .dat_i(fifo_dat_i),
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        .wr_i(fifo_wr),
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        .rd_i(fifo_rd),
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        .dat_o(fifo_dat_o),
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        .full_o(fifo_full),
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        .empty_o(fifo_empty)
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);
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//
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// fifo_rd
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//
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always @(posedge clk or posedge rst)
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        if (rst)
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                outstanding_store <=  1'b0;
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        else if (sbbiu_ack_i)
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                outstanding_store <=  1'b0;
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        else if (sel_sb | fifo_wr)
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                outstanding_store <=  1'b1;
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//
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// fifo_wr_ack
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//
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always @(posedge clk or posedge rst)
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        if (rst)
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                fifo_wr_ack <=  1'b0;
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        else if (fifo_wr)
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                fifo_wr_ack <=  1'b1;
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        else
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                fifo_wr_ack <=  1'b0;
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`else   // !OR1200_SB_IMPLEMENTED
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assign sbbiu_dat_o = dcsb_dat_i;
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assign sbbiu_adr_o = dcsb_adr_i;
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assign sbbiu_cyc_o = dcsb_cyc_i;
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assign sbbiu_stb_o = dcsb_stb_i;
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assign sbbiu_we_o = dcsb_we_i;
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assign sbbiu_cab_o = dcsb_cab_i;
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assign sbbiu_sel_o = dcsb_sel_i;
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assign dcsb_dat_o = sbbiu_dat_i;
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assign dcsb_ack_o = sbbiu_ack_i;
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assign dcsb_err_o = sbbiu_err_i;
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`endif
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endmodule

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