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[/] [claw/] [trunk/] [or1200_cpu/] [or1200_spram_1024x32.v] - Blame information for rev 4

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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  Generic Single-Port Synchronous RAM                         ////
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////                                                              ////
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////  This file is part of memory library available from          ////
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////  http://www.opencores.org/cvsweb.shtml/generic_memories/     ////
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////                                                              ////
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////  Description                                                 ////
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////  This block is a wrapper with common single-port             ////
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////  synchronous memory interface for different                  ////
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////  types of ASIC and FPGA RAMs. Beside universal memory        ////
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////  interface it also provides behavioral model of generic      ////
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////  single-port synchronous RAM.                                ////
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////  It should be used in all OPENCORES designs that want to be  ////
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////  portable accross different target technologies and          ////
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////  independent of target memory.                               ////
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////                                                              ////
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////  Supported ASIC RAMs are:                                    ////
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////  - Artisan Single-Port Sync RAM                              ////
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////  - Avant! Two-Port Sync RAM (*)                              ////
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////  - Virage Single-Port Sync RAM                               ////
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////  - Virtual Silicon Single-Port Sync RAM                      ////
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////                                                              ////
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////  Supported FPGA RAMs are:                                    ////
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////  - Xilinx Virtex RAMB4_S16                                   ////
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////  - Altera LPM                                                ////
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////                                                              ////
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////  To Do:                                                      ////
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////   - xilinx rams need external tri-state logic                ////
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////   - fix avant! two-port ram                                  ////
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////   - add additional RAMs                                      ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Damjan Lampret, lampret@opencores.org                 ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
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// Revision 1.7  2004/04/05 08:29:57  lampret
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// Merged branch_qmem into main tree.
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//
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// Revision 1.3.4.2  2003/12/09 11:46:48  simons
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// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
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//
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// Revision 1.3.4.1  2003/07/08 15:36:37  lampret
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// Added embedded memory QMEM.
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//
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// Revision 1.3  2003/04/07 01:19:07  lampret
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// Added Altera LPM RAMs. Changed generic RAM output when OE inactive.
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//
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// Revision 1.2  2002/10/17 20:04:40  lampret
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// Added BIST scan. Special VS RAMs need to be used to implement BIST.
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//
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// Revision 1.1  2002/01/03 08:16:15  lampret
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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//
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// Revision 1.8  2001/11/02 18:57:14  lampret
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// Modified virtual silicon instantiations.
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//
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// Revision 1.7  2001/10/21 17:57:16  lampret
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// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
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//
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// Revision 1.6  2001/10/14 13:12:09  lampret
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// MP3 version.
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//
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// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
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// no message
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//
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// Revision 1.1  2001/08/09 13:39:33  lampret
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// Major clean-up.
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//
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// Revision 1.2  2001/07/30 05:38:02  lampret
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// Adding empty directories required by HDL coding guidelines
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//
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//
103
 
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// synopsys translate_off
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`include "timescale.v"
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// synopsys translate_on
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`include "or1200_defines.v"
108
 
109
module or1200_spram_1024x32(
110
`ifdef OR1200_BIST
111
        // RAM BIST
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        mbist_si_i, mbist_so_o, mbist_ctrl_i,
113
`endif
114
        // Generic synchronous single-port RAM interface
115
        clk, rst, ce, we, oe, addr, di, do
116
);
117
 
118
//
119
// Default address and data buses width
120
//
121
parameter aw = 10;
122
parameter dw = 32;
123
 
124
`ifdef OR1200_BIST
125
//
126
// RAM BIST
127
//
128
input mbist_si_i;
129
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
130
output mbist_so_o;
131
`endif
132
 
133
//
134
// Generic synchronous single-port RAM interface
135
//
136
input                   clk;    // Clock
137
input                   rst;    // Reset
138
input                   ce;     // Chip enable input
139
input                   we;     // Write enable input
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input                   oe;     // Output enable input
141
input   [aw-1:0] addr;   // address bus inputs
142
input   [dw-1:0] di;     // input data bus
143
output  [dw-1:0] do;     // output data bus
144
 
145
//
146
// Internal wires and registers
147
//
148
 
149
`ifdef OR1200_ARTISAN_SSP
150
`else
151
`ifdef OR1200_VIRTUALSILICON_SSP
152
`else
153
`ifdef OR1200_BIST
154
assign mbist_so_o = mbist_si_i;
155
`endif
156
`endif
157
`endif
158
 
159
`ifdef OR1200_ARTISAN_SSP
160
 
161
//
162
// Instantiation of ASIC memory:
163
//
164
// Artisan Synchronous Single-Port RAM (ra1sh)
165
//
166
`ifdef UNUSED
167
art_hssp_1024x32 #(dw, 1<<aw, aw) artisan_ssp(
168
`else
169
`ifdef OR1200_BIST
170
art_hssp_1024x32_bist artisan_ssp(
171
`else
172
art_hssp_1024x32 artisan_ssp(
173
`endif
174
`endif
175
`ifdef OR1200_BIST
176
        // RAM BIST
177
        .mbist_si_i(mbist_si_i),
178
        .mbist_so_o(mbist_so_o),
179
        .mbist_ctrl_i(mbist_ctrl_i),
180
`endif
181
        .CLK(clk),
182
        .CEN(~ce),
183
        .WEN(~we),
184
        .A(addr),
185
        .D(di),
186
        .OEN(~oe),
187
        .Q(do)
188
);
189
 
190
`else
191
 
192
`ifdef OR1200_AVANT_ATP
193
 
194
//
195
// Instantiation of ASIC memory:
196
//
197
// Avant! Asynchronous Two-Port RAM
198
//
199
avant_atp avant_atp(
200
        .web(~we),
201
        .reb(),
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        .oeb(~oe),
203
        .rcsb(),
204
        .wcsb(),
205
        .ra(addr),
206
        .wa(addr),
207
        .di(di),
208
        .do(do)
209
);
210
 
211
`else
212
 
213
`ifdef OR1200_VIRAGE_SSP
214
 
215
//
216
// Instantiation of ASIC memory:
217
//
218
// Virage Synchronous 1-port R/W RAM
219
//
220
virage_ssp virage_ssp(
221
        .clk(clk),
222
        .adr(addr),
223
        .d(di),
224
        .we(we),
225
        .oe(oe),
226
        .me(ce),
227
        .q(do)
228
);
229
 
230
`else
231
 
232
`ifdef OR1200_VIRTUALSILICON_SSP
233
 
234
//
235
// Instantiation of ASIC memory:
236
//
237
// Virtual Silicon Single-Port Synchronous SRAM
238
//
239
`ifdef UNUSED
240
vs_hdsp_1024x32 #(1<<aw, aw-1, dw-1) vs_ssp(
241
`else
242
`ifdef OR1200_BIST
243
vs_hdsp_1024x32_bist vs_ssp(
244
`else
245
vs_hdsp_1024x32 vs_ssp(
246
`endif
247
`endif
248
`ifdef OR1200_BIST
249
        // RAM BIST
250
        .mbist_si_i(mbist_si_i),
251
        .mbist_so_o(mbist_so_o),
252
        .mbist_ctrl_i(mbist_ctrl_i),
253
`endif
254
        .CK(clk),
255
        .ADR(addr),
256
        .DI(di),
257
        .WEN(~we),
258
        .CEN(~ce),
259
        .OEN(~oe),
260
        .DOUT(do)
261
);
262
 
263
`else
264
 
265
`ifdef OR1200_XILINX_RAMB4
266
 
267
//
268
// Instantiation of FPGA memory:
269
//
270
// Virtex/Spartan2
271
//
272
 
273
//
274
// Block 0
275
//
276
RAMB4_S4 ramb4_s4_0(
277
        .CLK(clk),
278
        .RST(rst),
279
        .ADDR(addr),
280
        .DI(di[3:0]),
281
        .EN(ce),
282
        .WE(we),
283
        .DO(do[3:0])
284
);
285
 
286
//
287
// Block 1
288
//
289
RAMB4_S4 ramb4_s4_1(
290
        .CLK(clk),
291
        .RST(rst),
292
        .ADDR(addr),
293
        .DI(di[7:4]),
294
        .EN(ce),
295
        .WE(we),
296
        .DO(do[7:4])
297
);
298
 
299
//
300
// Block 2
301
//
302
RAMB4_S4 ramb4_s4_2(
303
        .CLK(clk),
304
        .RST(rst),
305
        .ADDR(addr),
306
        .DI(di[11:8]),
307
        .EN(ce),
308
        .WE(we),
309
        .DO(do[11:8])
310
);
311
 
312
//
313
// Block 3
314
//
315
RAMB4_S4 ramb4_s4_3(
316
        .CLK(clk),
317
        .RST(rst),
318
        .ADDR(addr),
319
        .DI(di[15:12]),
320
        .EN(ce),
321
        .WE(we),
322
        .DO(do[15:12])
323
);
324
 
325
//
326
// Block 4
327
//
328
RAMB4_S4 ramb4_s4_4(
329
        .CLK(clk),
330
        .RST(rst),
331
        .ADDR(addr),
332
        .DI(di[19:16]),
333
        .EN(ce),
334
        .WE(we),
335
        .DO(do[19:16])
336
);
337
 
338
//
339
// Block 5
340
//
341
RAMB4_S4 ramb4_s4_5(
342
        .CLK(clk),
343
        .RST(rst),
344
        .ADDR(addr),
345
        .DI(di[23:20]),
346
        .EN(ce),
347
        .WE(we),
348
        .DO(do[23:20])
349
);
350
 
351
//
352
// Block 6
353
//
354
RAMB4_S4 ramb4_s4_6(
355
        .CLK(clk),
356
        .RST(rst),
357
        .ADDR(addr),
358
        .DI(di[27:24]),
359
        .EN(ce),
360
        .WE(we),
361
        .DO(do[27:24])
362
);
363
 
364
//
365
// Block 7
366
//
367
RAMB4_S4 ramb4_s4_7(
368
        .CLK(clk),
369
        .RST(rst),
370
        .ADDR(addr),
371
        .DI(di[31:28]),
372
        .EN(ce),
373
        .WE(we),
374
        .DO(do[31:28])
375
);
376
 
377
`else
378
 
379
`ifdef OR1200_ALTERA_LPM
380
 
381
//
382
// Instantiation of FPGA memory:
383
//
384
// Altera LPM
385
//
386
// Added By Jamil Khatib
387
//
388
 
389
wire    wr;
390
 
391
assign  wr = ce & we;
392
 
393
initial $display("Using Altera LPM.");
394
 
395
lpm_ram_dq lpm_ram_dq_component (
396
        .address(addr),
397
        .inclock(clk),
398
        .outclock(clk),
399
        .data(di),
400
        .we(wr),
401
        .q(do)
402
);
403
 
404
defparam lpm_ram_dq_component.lpm_width = dw,
405
        lpm_ram_dq_component.lpm_widthad = aw,
406
        lpm_ram_dq_component.lpm_indata = "REGISTERED",
407
        lpm_ram_dq_component.lpm_address_control = "REGISTERED",
408
        lpm_ram_dq_component.lpm_outdata = "UNREGISTERED",
409
        lpm_ram_dq_component.lpm_hint = "USE_EAB=ON";
410
        // examplar attribute lpm_ram_dq_component NOOPT TRUE
411
 
412
`else
413
 
414
 
415
 
416
//
417
// Generic single-port synchronous RAM model
418
//
419
 
420
//
421
// Generic RAM's registers and wires
422
//
423
reg     [dw-1:0] mem [(1<<aw)-1:0];       // RAM content
424
reg     [dw-1:0] do_reg;                 // RAM data output register
425
integer iI;
426
 
427
// This part is used to put some data n the memory
428
// this is NOT synthesizable so please comment it out before running it
429
// in this module we will the memory with nops
430
`ifdef BALAJI_TESTING
431
initial begin
432
  for (iI = 0; iI < 1024 ; iI = iI + 1)
433
     mem[iI] = 32'b0001_0101_0000_0000_0000_0000_0000_0000;
434
end
435
`endif
436
//
437
// Data output drivers
438
//
439
assign do = (oe) ? do_reg : {dw{1'b0}};
440
 
441
 
442
//
443
// RAM read and write
444
//
445
always @(posedge clk)
446
        if (ce && !we)
447
                do_reg <= #1 mem[addr];
448
        else if (ce && we)
449
                mem[addr] <= #1 di;
450
 
451
`endif  // !OR1200_ALTERA_LPM
452
`endif  // !OR1200_XILINX_RAMB4_S16
453
`endif  // !OR1200_VIRTUALSILICON_SSP
454
`endif  // !OR1200_VIRAGE_SSP
455
`endif  // !OR1200_AVANT_ATP
456
`endif  // !OR1200_ARTISAN_SSP
457
 
458
endmodule

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