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[/] [claw/] [trunk/] [or1200_cpu/] [or1200_spram_256x21.v] - Blame information for rev 4

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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  Generic Single-Port Synchronous RAM                         ////
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////                                                              ////
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////  This file is part of memory library available from          ////
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////  http://www.opencores.org/cvsweb.shtml/generic_memories/     ////
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////                                                              ////
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////  Description                                                 ////
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////  This block is a wrapper with common single-port             ////
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////  synchronous memory interface for different                  ////
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////  types of ASIC and FPGA RAMs. Beside universal memory        ////
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////  interface it also provides behavioral model of generic      ////
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////  single-port synchronous RAM.                                ////
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////  It should be used in all OPENCORES designs that want to be  ////
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////  portable accross different target technologies and          ////
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////  independent of target memory.                               ////
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////                                                              ////
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////  Supported ASIC RAMs are:                                    ////
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////  - Artisan Single-Port Sync RAM                              ////
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////  - Avant! Two-Port Sync RAM (*)                              ////
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////  - Virage Single-Port Sync RAM                               ////
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////  - Virtual Silicon Single-Port Sync RAM                      ////
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////                                                              ////
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////  Supported FPGA RAMs are:                                    ////
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////  - Xilinx Virtex RAMB4_S16                                   ////
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////  - Altera LPM                                                ////
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////                                                              ////
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////  To Do:                                                      ////
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////   - xilinx rams need external tri-state logic                ////
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////   - fix avant! two-port ram                                  ////
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////   - add additional RAMs                                      ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Damjan Lampret, lampret@opencores.org                 ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
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// Revision 1.7  2004/04/05 08:29:57  lampret
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// Merged branch_qmem into main tree.
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//
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// Revision 1.3.4.2  2003/12/09 11:46:48  simons
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// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
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//
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// Revision 1.3.4.1  2003/07/08 15:36:37  lampret
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// Added embedded memory QMEM.
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//
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// Revision 1.3  2003/04/07 01:19:07  lampret
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// Added Altera LPM RAMs. Changed generic RAM output when OE inactive.
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//
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// Revision 1.2  2002/10/17 20:04:40  lampret
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// Added BIST scan. Special VS RAMs need to be used to implement BIST.
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//
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// Revision 1.1  2002/01/03 08:16:15  lampret
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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//
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// Revision 1.10  2001/11/27 21:24:04  lampret
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// Changed instantiation name of VS RAMs.
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//
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// Revision 1.9  2001/11/27 19:45:04  lampret
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// Fixed VS RAM instantiation - again.
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//
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// Revision 1.8  2001/11/23 21:42:31  simons
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// Program counter divided to PPC and NPC.
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//
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// Revision 1.6  2001/10/21 17:57:16  lampret
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// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
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//
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// Revision 1.5  2001/10/14 13:12:09  lampret
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// MP3 version.
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//
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// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
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// no message
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//
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// Revision 1.1  2001/08/09 13:39:33  lampret
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// Major clean-up.
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//
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// Revision 1.2  2001/07/30 05:38:02  lampret
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// Adding empty directories required by HDL coding guidelines
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//
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//
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// synopsys translate_off
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`include "timescale.v"
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// synopsys translate_on
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`include "or1200_defines.v"
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module or1200_spram_256x21(
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`ifdef OR1200_BIST
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        // RAM BIST
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        mbist_si_i, mbist_so_o, mbist_ctrl_i,
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`endif
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        // Generic synchronous single-port RAM interface
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        clk, rst, ce, we, oe, addr, di, do
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);
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//
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// Default address and data buses width
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//
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parameter aw = 8;
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parameter dw = 21;
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`ifdef OR1200_BIST
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//
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// RAM BIST
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//
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input mbist_si_i;
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input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
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output mbist_so_o;
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`endif
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//
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// Generic synchronous single-port RAM interface
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//
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input                   clk;    // Clock
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input                   rst;    // Reset
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input                   ce;     // Chip enable input
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input                   we;     // Write enable input
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input                   oe;     // Output enable input
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input   [aw-1:0] addr;   // address bus inputs
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input   [dw-1:0] di;     // input data bus
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output  [dw-1:0] do;     // output data bus
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//
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// Internal wires and registers
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//
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wire    [10:0]           unconnected;
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`ifdef OR1200_ARTISAN_SSP
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`else
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`ifdef OR1200_VIRTUALSILICON_SSP
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`else
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`ifdef OR1200_BIST
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assign mbist_so_o = mbist_si_i;
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`endif
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`endif
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`endif
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`ifdef OR1200_ARTISAN_SSP
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//
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// Instantiation of ASIC memory:
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//
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// Artisan Synchronous Single-Port RAM (ra1sh)
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//
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`ifdef UNUSED
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art_hssp_256x21 #(dw, 1<<aw, aw) artisan_ssp(
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`else
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`ifdef OR1200_BIST
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art_hssp_256x21_bist artisan_ssp(
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`else
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art_hssp_256x21 artisan_ssp(
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`endif
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`endif
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`ifdef OR1200_BIST
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        // RAM BIST
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        .mbist_si_i(mbist_si_i),
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        .mbist_so_o(mbist_so_o),
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        .mbist_ctrl_i(mbist_ctrl_i),
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`endif
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        .CLK(clk),
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        .CEN(~ce),
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        .WEN(~we),
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        .A(addr),
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        .D(di),
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        .OEN(~oe),
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        .Q(do)
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);
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`else
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`ifdef OR1200_AVANT_ATP
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//
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// Instantiation of ASIC memory:
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//
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// Avant! Asynchronous Two-Port RAM
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//
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avant_atp avant_atp(
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        .web(~we),
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        .reb(),
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        .oeb(~oe),
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        .rcsb(),
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        .wcsb(),
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        .ra(addr),
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        .wa(addr),
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        .di(di),
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        .do(do)
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);
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`else
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`ifdef OR1200_VIRAGE_SSP
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//
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// Instantiation of ASIC memory:
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//
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// Virage Synchronous 1-port R/W RAM
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//
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virage_ssp virage_ssp(
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        .clk(clk),
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        .adr(addr),
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        .d(di),
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        .we(we),
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        .oe(oe),
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        .me(ce),
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        .q(do)
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);
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`else
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`ifdef OR1200_VIRTUALSILICON_SSP
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//
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// Instantiation of ASIC memory:
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//
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// Virtual Silicon Single-Port Synchronous SRAM
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//
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`ifdef UNUSED
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vs_hdsp_256x21 #(1<<aw, aw-1, dw-1) vs_ssp(
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`else
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`ifdef OR1200_BIST
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vs_hdsp_256x21_bist vs_ssp(
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`else
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vs_hdsp_256x21 vs_ssp(
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`endif
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`endif
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`ifdef OR1200_BIST
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        // RAM BIST
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        .mbist_si_i(mbist_si_i),
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        .mbist_so_o(mbist_so_o),
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        .mbist_ctrl_i(mbist_ctrl_i),
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`endif
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        .CK(clk),
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        .ADR(addr),
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        .DI(di),
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        .WEN(~we),
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        .CEN(~ce),
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        .OEN(~oe),
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        .DOUT(do)
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);
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`else
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`ifdef OR1200_XILINX_RAMB4
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//
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// Instantiation of FPGA memory:
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//
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// Virtex/Spartan2
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//
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//
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// Block 0
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//
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RAMB4_S16 ramb4_s16_0(
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        .CLK(clk),
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        .RST(rst),
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        .ADDR(addr),
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        .DI(di[15:0]),
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        .EN(ce),
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        .WE(we),
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        .DO(do[15:0])
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);
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//
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// Block 1
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//
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RAMB4_S16 ramb4_s16_1(
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        .CLK(clk),
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        .RST(rst),
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        .ADDR(addr),
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        .DI({11'b00000000000, di[20:16]}),
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        .EN(ce),
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        .WE(we),
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        .DO({unconnected, do[20:16]})
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);
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`else
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`ifdef OR1200_ALTERA_LPM
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//
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// Instantiation of FPGA memory:
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//
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// Altera LPM
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//
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// Added By Jamil Khatib
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//
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wire    wr;
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assign  wr = ce & we;
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initial $display("Using Altera LPM.");
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lpm_ram_dq lpm_ram_dq_component (
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        .address(addr),
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        .inclock(clk),
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        .outclock(clk),
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        .data(di),
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        .we(wr),
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        .q(do)
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);
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defparam lpm_ram_dq_component.lpm_width = dw,
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        lpm_ram_dq_component.lpm_widthad = aw,
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        lpm_ram_dq_component.lpm_indata = "REGISTERED",
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        lpm_ram_dq_component.lpm_address_control = "REGISTERED",
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        lpm_ram_dq_component.lpm_outdata = "UNREGISTERED",
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        lpm_ram_dq_component.lpm_hint = "USE_EAB=ON";
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        // examplar attribute lpm_ram_dq_component NOOPT TRUE
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341
`else
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//
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// Generic single-port synchronous RAM model
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//
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347
//
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// Generic RAM's registers and wires
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//
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reg     [dw-1:0] mem [(1<<aw)-1:0];       // RAM content
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reg     [dw-1:0] do_reg;                 // RAM data output register
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353
//
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// Data output drivers
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//
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assign do = (oe) ? do_reg : {dw{1'b0}};
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358
//
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// RAM read and write
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//
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always @(posedge clk)
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        if (ce && !we)
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                do_reg <= #1 mem[addr];
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        else if (ce && we)
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                mem[addr] <= #1 di;
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`endif  // !OR1200_ALTERA_LPM
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`endif  // !OR1200_XILINX_RAMB4_S16
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`endif  // !OR1200_VIRTUALSILICON_SSP
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`endif  // !OR1200_VIRAGE_SSP
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`endif  // !OR1200_AVANT_ATP
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`endif  // !OR1200_ARTISAN_SSP
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endmodule

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