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[/] [claw/] [trunk/] [or1200_cpu/] [or1200_sprs.v] - Blame information for rev 4

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//////////////////////////////////////////////////////////////////////
2
////                                                              ////
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////  OR1200's interface to SPRs                                  ////
4
////                                                              ////
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////  This file is part of the OpenRISC 1200 project              ////
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////  http://www.opencores.org/cores/or1k/                        ////
7
////                                                              ////
8
////  Description                                                 ////
9
////  Decoding of SPR addresses and access to SPRs                ////
10
////                                                              ////
11
////  To Do:                                                      ////
12
////   - make it smaller and faster                               ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Damjan Lampret, lampret@opencores.org                 ////
16
////                                                              ////
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////  Modified by:                                                ////
18
////      - Balaji V. Iyer, bviyer@ncsu.edu                       ////
19
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
26
//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
30
//// Public License as published by the Free Software Foundation; ////
31
//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
41
//// Public License along with this source; if not, download it   ////
42
//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
44
//////////////////////////////////////////////////////////////////////
45
//
46
// CVS Revision History
47
//
48
// $Log: not supported by cvs2svn $
49
// Revision 1.11  2004/04/05 08:29:57  lampret
50
// Merged branch_qmem into main tree.
51
//
52
// Revision 1.9.4.1  2003/12/17 13:43:38  simons
53
// Exception prefix configuration changed.
54
//
55
// Revision 1.9  2002/09/07 05:42:02  lampret
56
// Added optional SR[CY]. Added define to enable additional (compare) flag modifiers. Defines are OR1200_IMPL_ADDC and OR1200_ADDITIONAL_FLAG_MODIFIERS.
57
//
58
// Revision 1.8  2002/08/28 01:44:25  lampret
59
// Removed some commented RTL. Fixed SR/ESR flag bug.
60
//
61
// Revision 1.7  2002/03/29 15:16:56  lampret
62
// Some of the warnings fixed.
63
//
64
// Revision 1.6  2002/03/11 01:26:57  lampret
65
// Changed generation of SPR address. Now it is ORed from base and offset instead of a sum.
66
//
67
// Revision 1.5  2002/02/01 19:56:54  lampret
68
// Fixed combinational loops.
69
//
70
// Revision 1.4  2002/01/23 07:52:36  lampret
71
// Changed default reset values for SR and ESR to match or1ksim's. Fixed flop model in or1200_dpram_32x32 when OR1200_XILINX_RAM32X1D is defined.
72
//
73
// Revision 1.3  2002/01/19 09:27:49  lampret
74
// SR[TEE] should be zero after reset.
75
//
76
// Revision 1.2  2002/01/18 07:56:00  lampret
77
// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.
78
//
79
// Revision 1.1  2002/01/03 08:16:15  lampret
80
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
81
//
82
// Revision 1.12  2001/11/23 21:42:31  simons
83
// Program counter divided to PPC and NPC.
84
//
85
// Revision 1.11  2001/11/23 08:38:51  lampret
86
// Changed DSR/DRR behavior and exception detection.
87
//
88
// Revision 1.10  2001/11/12 01:45:41  lampret
89
// Moved flag bit into SR. Changed RF enable from constant enable to dynamic enable for read ports.
90
//
91
// Revision 1.9  2001/10/21 17:57:16  lampret
92
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
93
//
94
// Revision 1.8  2001/10/14 13:12:10  lampret
95
// MP3 version.
96
//
97
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
98
// no message
99
//
100
// Revision 1.3  2001/08/13 03:36:20  lampret
101
// Added cfg regs. Moved all defines into one defines.v file. More cleanup.
102
//
103
// Revision 1.2  2001/08/09 13:39:33  lampret
104
// Major clean-up.
105
//
106
// Revision 1.1  2001/07/20 00:46:21  lampret
107
// Development version of RTL. Libraries are missing.
108
//
109
//
110
 
111
// synopsys translate_off
112
`include "timescale.v"
113
// synopsys translate_on
114
`include "or1200_defines.v"
115
 
116
module or1200_sprs(
117
                // Clk & Rst
118
                clk, rst,
119
 
120
                // Internal CPU interface
121
                flagforw, flag_we, flag, cyforw, cy_we, carry,
122
                addrbase, addrofs, dat_i, alu_op, branch_op,
123
                epcr, eear, esr, except_started,
124
                to_wbmux, epcr_we, eear_we, esr_we, pc_we, sr_we, to_sr, sr,
125
                spr_dat_cfgr, spr_dat_rf, spr_dat_npc, spr_dat_ppc, spr_dat_mac,
126
                spr_dat_cfgr2, // bviyer
127
                // From/to other RISC units
128
                spr_dat_pic, spr_dat_tt, spr_dat_pm,
129
                spr_dat_dmmu, spr_dat_immu, spr_dat_du,
130
                spr_addr, spr_addr2, spr_dat_o, spr_cs, spr_we,
131
 
132
                du_addr, du_dat_du, du_read,
133
                du_write, du_dat_cpu,
134
                thread_in, thread_out
135
 
136
);
137
 
138
parameter width = 32; // `OR1200_OPERAND_WIDTH;
139
 
140
//
141
// I/O Ports
142
//
143
 
144
//
145
// Internal CPU interface
146
//
147
input                           clk;            // Clock
148
input                           rst;            // Reset
149
input                           flagforw;       // From ALU
150
input                           flag_we;        // From ALU
151
output                          flag;           // SR[F]
152
input                           cyforw;         // From ALU
153
input                           cy_we;          // From ALU
154
output                          carry;          // SR[CY]
155
input   [width-1:0]              addrbase;       // SPR base address
156
input   [15:0]                   addrofs;        // SPR offset
157
input   [width-1:0]              dat_i;          // SPR write data
158
input   [`OR1200_ALUOP_WIDTH-1:0]        alu_op;         // ALU operation
159
input   [`OR1200_BRANCHOP_WIDTH-1:0]     branch_op;      // Branch operation
160
input   [width-1:0]              epcr;           // EPCR0
161
input   [width-1:0]              eear;           // EEAR0
162
input   [`OR1200_SR_WIDTH-1:0]   esr;            // ESR0
163
input                           except_started; // Exception was started
164
output  [width-1:0]              to_wbmux;       // For l.mfspr
165
output                          epcr_we;        // EPCR0 write enable
166
output                          eear_we;        // EEAR0 write enable
167
output                          esr_we;         // ESR0 write enable
168
output                          pc_we;          // PC write enable
169
output                          sr_we;          // Write enable SR
170
output  [`OR1200_SR_WIDTH-1:0]   to_sr;          // Data to SR
171
output  [`OR1200_SR_WIDTH-1:0]   sr;             // SR
172
input   [31:0]                   spr_dat_cfgr;   // Data from CFGR
173
input   [31:0]                   spr_dat_cfgr2;  // Data from CFGR
174
input   [31:0]                   spr_dat_rf;     // Data from RF
175
input   [31:0]                   spr_dat_npc;    // Data from NPC
176
input   [31:0]                   spr_dat_ppc;    // Data from PPC   
177
input   [31:0]                   spr_dat_mac;    // Data from MAC
178
 
179
//
180
// To/from other RISC units
181
//
182
input   [31:0]                   spr_dat_pic;    // Data from PIC
183
input   [31:0]                   spr_dat_tt;     // Data from TT
184
input   [31:0]                   spr_dat_pm;     // Data from PM
185
input   [31:0]                   spr_dat_dmmu;   // Data from DMMU
186
input   [31:0]                   spr_dat_immu;   // Data from IMMU
187
input   [31:0]                   spr_dat_du;     // Data from DU
188
output  [31:0]                   spr_addr;       // SPR Address
189
output  [31:0]                   spr_addr2;      // SPR Address
190
output  [31:0]                   spr_dat_o;      // Data to unit
191
output  [31:0]                   spr_cs;         // Unit select
192
output                          spr_we;         // SPR write enable
193
 
194
//
195
// To/from Debug Unit
196
//
197
input   [width-1:0]              du_addr;        // Address
198
input   [width-1:0]              du_dat_du;      // Data from DU to SPRS
199
input                           du_read;        // Read qualifier
200
input                           du_write;       // Write qualifier
201
output  [width-1:0]              du_dat_cpu;     // Data from SPRS to DU
202
 
203
// bviyer
204
input [2:0]      thread_in;
205
output [2:0]     thread_out;
206
//
207
// Internal regs & wires
208
//
209
reg     [`OR1200_SR_WIDTH-1:0]           sr;             // SR
210
reg                             write_spr;      // Write SPR
211
reg                             read_spr;       // Read SPR
212
reg     [width-1:0]              to_wbmux;       // For l.mfspr
213
wire                            cfgr_sel;       // Select for cfg regs
214
wire                            rf_sel;         // Select for RF
215
wire                            npc_sel;        // Select for NPC
216
wire                            ppc_sel;        // Select for PPC
217
wire                            sr_sel;         // Select for SR        
218
wire                            epcr_sel;       // Select for EPCR0
219
wire                            eear_sel;       // Select for EEAR0
220
wire                            esr_sel;        // Select for ESR0
221
wire    [31:0]                   sys_data;       // Read data from system SPRs
222
wire                            du_access;      // Debug unit access
223
wire    [`OR1200_ALUOP_WIDTH-1:0]        sprs_op;        // ALU operation
224
reg     [31:0]                   unqualified_cs; // Unqualified chip selects
225
 
226
 
227
 
228
//
229
// Decide if it is debug unit access
230
//
231
assign du_access = du_read | du_write;
232
 
233
//
234
// Generate sprs opcode
235
//
236
assign sprs_op = du_write ? `OR1200_ALUOP_MTSR : du_read ? `OR1200_ALUOP_MFSR : alu_op;
237
 
238
//
239
// Generate SPR address from base address and offset
240
// OR from debug unit address
241
//
242
assign spr_addr = du_access ? du_addr : addrbase | {16'h0000, addrofs};
243
assign spr_addr2 = du_access ? du_addr : addrbase | {16'h0000, addrofs};
244
 
245
//
246
// SPR is written by debug unit or by l.mtspr
247
//
248
assign spr_dat_o = du_write ? du_dat_du : dat_i;
249
 
250
//
251
// debug unit data input:
252
//  - write into debug unit SPRs by debug unit itself
253
//  - read of SPRS by debug unit
254
//  - write into debug unit SPRs by l.mtspr
255
//
256
assign du_dat_cpu = du_write ? du_dat_du : du_read ? to_wbmux : dat_i;
257
 
258
//
259
// Write into SPRs when l.mtspr
260
//
261
assign spr_we = du_write | write_spr;
262
 
263
//
264
// Qualify chip selects
265
//
266
assign spr_cs = unqualified_cs & {32{read_spr | write_spr}};
267
 
268
//
269
// Decoding of groups
270
//
271
always @(spr_addr)
272
        case (spr_addr[`OR1200_SPR_GROUP_BITS]) // synopsys parallel_case
273
                `OR1200_SPR_GROUP_WIDTH'd00: unqualified_cs = 32'b00000000_00000000_00000000_00000001;
274
                `OR1200_SPR_GROUP_WIDTH'd01: unqualified_cs = 32'b00000000_00000000_00000000_00000010;
275
                `OR1200_SPR_GROUP_WIDTH'd02: unqualified_cs = 32'b00000000_00000000_00000000_00000100;
276
                `OR1200_SPR_GROUP_WIDTH'd03: unqualified_cs = 32'b00000000_00000000_00000000_00001000;
277
                `OR1200_SPR_GROUP_WIDTH'd04: unqualified_cs = 32'b00000000_00000000_00000000_00010000;
278
                `OR1200_SPR_GROUP_WIDTH'd05: unqualified_cs = 32'b00000000_00000000_00000000_00100000;
279
                `OR1200_SPR_GROUP_WIDTH'd06: unqualified_cs = 32'b00000000_00000000_00000000_01000000;
280
                `OR1200_SPR_GROUP_WIDTH'd07: unqualified_cs = 32'b00000000_00000000_00000000_10000000;
281
                `OR1200_SPR_GROUP_WIDTH'd08: unqualified_cs = 32'b00000000_00000000_00000001_00000000;
282
                `OR1200_SPR_GROUP_WIDTH'd09: unqualified_cs = 32'b00000000_00000000_00000010_00000000;
283
                `OR1200_SPR_GROUP_WIDTH'd10: unqualified_cs = 32'b00000000_00000000_00000100_00000000;
284
                `OR1200_SPR_GROUP_WIDTH'd11: unqualified_cs = 32'b00000000_00000000_00001000_00000000;
285
                `OR1200_SPR_GROUP_WIDTH'd12: unqualified_cs = 32'b00000000_00000000_00010000_00000000;
286
                `OR1200_SPR_GROUP_WIDTH'd13: unqualified_cs = 32'b00000000_00000000_00100000_00000000;
287
                `OR1200_SPR_GROUP_WIDTH'd14: unqualified_cs = 32'b00000000_00000000_01000000_00000000;
288
                `OR1200_SPR_GROUP_WIDTH'd15: unqualified_cs = 32'b00000000_00000000_10000000_00000000;
289
                `OR1200_SPR_GROUP_WIDTH'd16: unqualified_cs = 32'b00000000_00000001_00000000_00000000;
290
                `OR1200_SPR_GROUP_WIDTH'd17: unqualified_cs = 32'b00000000_00000010_00000000_00000000;
291
                `OR1200_SPR_GROUP_WIDTH'd18: unqualified_cs = 32'b00000000_00000100_00000000_00000000;
292
                `OR1200_SPR_GROUP_WIDTH'd19: unqualified_cs = 32'b00000000_00001000_00000000_00000000;
293
                `OR1200_SPR_GROUP_WIDTH'd20: unqualified_cs = 32'b00000000_00010000_00000000_00000000;
294
                `OR1200_SPR_GROUP_WIDTH'd21: unqualified_cs = 32'b00000000_00100000_00000000_00000000;
295
                `OR1200_SPR_GROUP_WIDTH'd22: unqualified_cs = 32'b00000000_01000000_00000000_00000000;
296
                `OR1200_SPR_GROUP_WIDTH'd23: unqualified_cs = 32'b00000000_10000000_00000000_00000000;
297
                `OR1200_SPR_GROUP_WIDTH'd24: unqualified_cs = 32'b00000001_00000000_00000000_00000000;
298
                `OR1200_SPR_GROUP_WIDTH'd25: unqualified_cs = 32'b00000010_00000000_00000000_00000000;
299
                `OR1200_SPR_GROUP_WIDTH'd26: unqualified_cs = 32'b00000100_00000000_00000000_00000000;
300
                `OR1200_SPR_GROUP_WIDTH'd27: unqualified_cs = 32'b00001000_00000000_00000000_00000000;
301
                `OR1200_SPR_GROUP_WIDTH'd28: unqualified_cs = 32'b00010000_00000000_00000000_00000000;
302
                `OR1200_SPR_GROUP_WIDTH'd29: unqualified_cs = 32'b00100000_00000000_00000000_00000000;
303
                `OR1200_SPR_GROUP_WIDTH'd30: unqualified_cs = 32'b01000000_00000000_00000000_00000000;
304
                `OR1200_SPR_GROUP_WIDTH'd31: unqualified_cs = 32'b10000000_00000000_00000000_00000000;
305
        endcase
306
 
307
//
308
// SPRs System Group
309
//
310
 
311
//
312
// What to write into SR
313
//
314
assign to_sr[`OR1200_SR_FO:`OR1200_SR_OV] =
315
                (branch_op == `OR1200_BRANCHOP_RFE) ? esr[`OR1200_SR_FO:`OR1200_SR_OV] :
316
                (write_spr && sr_sel) ? {1'b1, spr_dat_o[`OR1200_SR_FO-1:`OR1200_SR_OV]}:
317
                sr[`OR1200_SR_FO:`OR1200_SR_OV];
318
assign to_sr[`OR1200_SR_CY] =
319
                (branch_op == `OR1200_BRANCHOP_RFE) ? esr[`OR1200_SR_CY] :
320
                cy_we ? cyforw :
321
                (write_spr && sr_sel) ? spr_dat_o[`OR1200_SR_CY] :
322
                sr[`OR1200_SR_CY];
323
assign to_sr[`OR1200_SR_F] =
324
                (branch_op == `OR1200_BRANCHOP_RFE) ? esr[`OR1200_SR_F] :
325
                flag_we ? flagforw :
326
                (write_spr && sr_sel) ? spr_dat_o[`OR1200_SR_F] :
327
                sr[`OR1200_SR_F];
328
assign to_sr[`OR1200_SR_CE:`OR1200_SR_SM] =
329
                (branch_op == `OR1200_BRANCHOP_RFE) ? esr[`OR1200_SR_CE:`OR1200_SR_SM] :
330
                (write_spr && sr_sel) ? spr_dat_o[`OR1200_SR_CE:`OR1200_SR_SM]:
331
                sr[`OR1200_SR_CE:`OR1200_SR_SM];
332
 
333
//
334
// Selects for system SPRs
335
//
336
assign cfgr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:4] == `OR1200_SPR_CFGR));
337
assign rf_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:5] == `OR1200_SPR_RF));
338
assign npc_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_NPC));
339
assign ppc_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_PPC));
340
assign sr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_SR));
341
assign epcr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_EPCR));
342
assign eear_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_EEAR));
343
assign esr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_ESR));
344
 
345
//
346
// Write enables for system SPRs
347
//
348
assign sr_we = (write_spr && sr_sel) | (branch_op == `OR1200_BRANCHOP_RFE) | flag_we | cy_we;
349
assign pc_we = (write_spr && (npc_sel | ppc_sel));
350
assign epcr_we = (write_spr && epcr_sel);
351
assign eear_we = (write_spr && eear_sel);
352
assign esr_we = (write_spr && esr_sel);
353
 
354
//
355
// Output from system SPRs
356
//
357
assign sys_data = (spr_dat_cfgr & {32{read_spr & cfgr_sel}}) |
358
                  (spr_dat_cfgr2 & {32{read_spr & cfgr_sel}}) |
359
                  (spr_dat_rf & {32{read_spr & rf_sel}}) |
360
                  (spr_dat_npc & {32{read_spr & npc_sel}}) |
361
                  (spr_dat_ppc & {32{read_spr & ppc_sel}}) |
362
                  ({{32-`OR1200_SR_WIDTH{1'b0}},sr} & {32{read_spr & sr_sel}}) |
363
                  (epcr & {32{read_spr & epcr_sel}}) |
364
                  (eear & {32{read_spr & eear_sel}}) |
365
                  ({{32-`OR1200_SR_WIDTH{1'b0}},esr} & {32{read_spr & esr_sel}});
366
 
367
//
368
// Flag alias
369
//
370
assign flag = sr[`OR1200_SR_F];
371
 
372
//
373
// Carry alias
374
//
375
assign carry = sr[`OR1200_SR_CY];
376
 
377
//
378
// Supervision register
379
//
380
always @(posedge clk or posedge rst)
381
        if (rst)
382
                sr <=  {1'b1, `OR1200_SR_EPH_DEF, {`OR1200_SR_WIDTH-3{1'b0}}, 1'b1};
383
        else if (except_started) begin
384
                sr[`OR1200_SR_SM]  <=  1'b1;
385
                sr[`OR1200_SR_TEE] <=  1'b0;
386
                sr[`OR1200_SR_IEE] <=  1'b0;
387
                sr[`OR1200_SR_DME] <=  1'b0;
388
                sr[`OR1200_SR_IME] <=  1'b0;
389
        end
390
        else if (sr_we)
391
                sr <=  to_sr[`OR1200_SR_WIDTH-1:0];
392
 
393
//
394
// MTSPR/MFSPR interface
395
//
396
always @(sprs_op or spr_addr or sys_data or spr_dat_mac or spr_dat_pic or spr_dat_pm or
397
        spr_dat_dmmu or spr_dat_immu or spr_dat_du or spr_dat_tt) begin
398
        case (sprs_op)  // synopsys parallel_case
399
                `OR1200_ALUOP_MTSR : begin
400
                        write_spr = 1'b1;
401
                        read_spr = 1'b0;
402
                        to_wbmux = 32'b0;
403
                end
404
                `OR1200_ALUOP_MFSR : begin
405
                        casex (spr_addr[`OR1200_SPR_GROUP_BITS]) // synopsys parallel_case
406
                                `OR1200_SPR_GROUP_TT:
407
                                        to_wbmux = spr_dat_tt;
408
                                `OR1200_SPR_GROUP_PIC:
409
                                        to_wbmux = spr_dat_pic;
410
                                `OR1200_SPR_GROUP_PM:
411
                                        to_wbmux = spr_dat_pm;
412
                                `OR1200_SPR_GROUP_DMMU:
413
                                        to_wbmux = spr_dat_dmmu;
414
                                `OR1200_SPR_GROUP_IMMU:
415
                                        to_wbmux = spr_dat_immu;
416
                                `OR1200_SPR_GROUP_MAC:
417
                                        to_wbmux = spr_dat_mac;
418
                                `OR1200_SPR_GROUP_DU:
419
                                        to_wbmux = spr_dat_du;
420
                                `OR1200_SPR_GROUP_SYS:
421
                                        to_wbmux = sys_data;
422
                                default:
423
                                        to_wbmux = 32'b0;
424
                        endcase
425
                        write_spr = 1'b0;
426
                        read_spr = 1'b1;
427
                end
428
                default : begin
429
                        write_spr = 1'b0;
430
                        read_spr = 1'b0;
431
                        to_wbmux = 32'b0;
432
                end
433
        endcase
434
end
435
assign thread_out = thread_in;
436
endmodule

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