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[/] [claw/] [trunk/] [or1200_cpu/] [or1200_top.v] - Blame information for rev 4

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//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  OR1200 Top Level                                            ////
4
////                                                              ////
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////  This file is part of the OpenRISC 1200 project              ////
6
////  http://www.opencores.org/cores/or1k/                        ////
7
////                                                              ////
8
////  Description                                                 ////
9
////  OR1200 Top Level                                            ////
10
////                                                              ////
11
////  To Do:                                                      ////
12
////   - make it smaller and faster                               ////
13
////                                                              ////
14
////  Author(s):                                                  ////
15
////      - Damjan Lampret, lampret@opencores.org                 ////
16
////  Modified by:                                                ////
17
////      - Balaji V. Iyer, bviyer@ncsu.edu                       ////
18
//////////////////////////////////////////////////////////////////////
19
////                                                              ////
20
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
21
////                                                              ////
22
//// This source file may be used and distributed without         ////
23
//// restriction provided that this copyright statement is not    ////
24
//// removed from the file and that any derivative work contains  ////
25
//// the original copyright notice and the associated disclaimer. ////
26
////                                                              ////
27
//// This source file is free software; you can redistribute it   ////
28
//// and/or modify it under the terms of the GNU Lesser General   ////
29
//// Public License as published by the Free Software Foundation; ////
30
//// either version 2.1 of the License, or (at your option) any   ////
31
//// later version.                                               ////
32
////                                                              ////
33
//// This source is distributed in the hope that it will be       ////
34
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
35
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
36
//// PURPOSE.  See the GNU Lesser General Public License for more ////
37
//// details.                                                     ////
38
////                                                              ////
39
//// You should have received a copy of the GNU Lesser General    ////
40
//// Public License along with this source; if not, download it   ////
41
//// from http://www.opencores.org/lgpl.shtml                     ////
42
////                                                              ////
43
//////////////////////////////////////////////////////////////////////
44
//
45
// CVS Revision History
46
//
47
// $Log: not supported by cvs2svn $
48
// Revision 1.12  2004/04/05 08:29:57  lampret
49
// Merged branch_qmem into main tree.
50
//
51
// Revision 1.10.4.9  2004/02/11 01:40:11  lampret
52
// preliminary HW breakpoints support in debug unit (by default disabled). To enable define OR1200_DU_HWBKPTS.
53
//
54
// Revision 1.10.4.8  2004/01/17 21:14:14  simons
55
// Errors fixed.
56
//
57
// Revision 1.10.4.7  2004/01/17 19:06:38  simons
58
// Error fixed.
59
//
60
// Revision 1.10.4.6  2004/01/17 18:39:48  simons
61
// Error fixed.
62
//
63
// Revision 1.10.4.5  2004/01/15 06:46:38  markom
64
// interface to debug changed; no more opselect; stb-ack protocol
65
//
66
// Revision 1.10.4.4  2003/12/09 11:46:49  simons
67
// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
68
//
69
// Revision 1.10.4.3  2003/12/05 00:08:44  lampret
70
// Fixed instantiation name.
71
//
72
// Revision 1.10.4.2  2003/07/11 01:10:35  lampret
73
// Added three missing wire declarations. No functional changes.
74
//
75
// Revision 1.10.4.1  2003/07/08 15:36:37  lampret
76
// Added embedded memory QMEM.
77
//
78
// Revision 1.10  2002/12/08 08:57:56  lampret
79
// Added optional support for WB B3 specification (xwb_cti_o, xwb_bte_o). Made xwb_cab_o optional.
80
//
81
// Revision 1.9  2002/10/17 20:04:41  lampret
82
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
83
//
84
// Revision 1.8  2002/08/18 19:54:22  lampret
85
// Added store buffer.
86
//
87
// Revision 1.7  2002/07/14 22:17:17  lampret
88
// Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized.
89
//
90
// Revision 1.6  2002/03/29 15:16:56  lampret
91
// Some of the warnings fixed.
92
//
93
// Revision 1.5  2002/02/11 04:33:17  lampret
94
// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
95
//
96
// Revision 1.4  2002/02/01 19:56:55  lampret
97
// Fixed combinational loops.
98
//
99
// Revision 1.3  2002/01/28 01:16:00  lampret
100
// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
101
//
102
// Revision 1.2  2002/01/18 07:56:00  lampret
103
// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.
104
//
105
// Revision 1.1  2002/01/03 08:16:15  lampret
106
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
107
//
108
// Revision 1.13  2001/11/23 08:38:51  lampret
109
// Changed DSR/DRR behavior and exception detection.
110
//
111
// Revision 1.12  2001/11/20 00:57:22  lampret
112
// Fixed width of du_except.
113
//
114
// Revision 1.11  2001/11/18 08:36:28  lampret
115
// For GDB changed single stepping and disabled trap exception.
116
//
117
// Revision 1.10  2001/10/21 17:57:16  lampret
118
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
119
//
120
// Revision 1.9  2001/10/14 13:12:10  lampret
121
// MP3 version.
122
//
123
// Revision 1.1.1.1  2001/10/06 10:18:35  igorm
124
// no message
125
//
126
// Revision 1.4  2001/08/13 03:36:20  lampret
127
// Added cfg regs. Moved all defines into one defines.v file. More cleanup.
128
//
129
// Revision 1.3  2001/08/09 13:39:33  lampret
130
// Major clean-up.
131
//
132
// Revision 1.2  2001/07/22 03:31:54  lampret
133
// Fixed RAM's oen bug. Cache bypass under development.
134
//
135
// Revision 1.1  2001/07/20 00:46:21  lampret
136
// Development version of RTL. Libraries are missing.
137
//
138
//
139
 
140
// synopsys translate_off
141
`include "timescale.v"
142
// synopsys translate_on
143
`include "or1200_defines.v"
144
 
145
module or1200_top(
146
        // System
147
        clk_i, rst_i, pic_ints_i, clmode_i,
148
 
149
        // Instruction WISHBONE INTERFACE
150
        iwb_clk_i, iwb_rst_i, iwb_ack_i, iwb_err_i, iwb_rty_i, iwb_dat_i,
151
        iwb_cyc_o, iwb_adr_o, iwb_stb_o, iwb_we_o, iwb_sel_o, iwb_dat_o,
152
`ifdef OR1200_WB_CAB
153
        iwb_cab_o,
154
`endif
155
`ifdef OR1200_WB_B3
156
        iwb_cti_o, iwb_bte_o,
157
`endif
158
        // Data WISHBONE INTERFACE
159
        dwb_clk_i, dwb_rst_i, dwb_ack_i, dwb_err_i, dwb_rty_i, dwb_dat_i,
160
        dwb_cyc_o, dwb_adr_o, dwb_stb_o, dwb_we_o, dwb_sel_o, dwb_dat_o,
161
`ifdef OR1200_WB_CAB
162
        dwb_cab_o,
163
`endif
164
`ifdef OR1200_WB_B3
165
        dwb_cti_o, dwb_bte_o,
166
`endif
167
 
168
        // External Debug Interface
169
        dbg_stall_i, dbg_ewt_i, dbg_lss_o, dbg_is_o, dbg_wp_o, dbg_bp_o,
170
        dbg_stb_i, dbg_we_i, dbg_adr_i, dbg_dat_i, dbg_dat_o, dbg_ack_o,
171
 
172
`ifdef OR1200_BIST
173
        // RAM BIST
174
        mbist_si_i, mbist_so_o, mbist_ctrl_i,
175
`endif
176
        // Power Management
177
        pm_cpustall_i,
178
        pm_clksd_o, pm_dc_gate_o, pm_ic_gate_o, pm_dmmu_gate_o,
179
        pm_immu_gate_o, pm_tt_gate_o, pm_cpu_gate_o, pm_wakeup_o, pm_lvolt_o
180
 
181
);
182
 
183
parameter dw = `OR1200_OPERAND_WIDTH;
184
parameter aw = `OR1200_OPERAND_WIDTH;
185
parameter ppic_ints = `OR1200_PIC_INTS;
186
 
187
//
188
// I/O
189
//
190
 
191
//
192
// System
193
//
194
input                   clk_i;
195
input                   rst_i;
196
input   [1:0]            clmode_i;       // 00 WB=RISC, 01 WB=RISC/2, 10 N/A, 11 WB=RISC/4
197
input   [ppic_ints-1:0]  pic_ints_i;
198
 
199
//
200
// Instruction WISHBONE interface
201
//
202
input                   iwb_clk_i;      // clock input
203
input                   iwb_rst_i;      // reset input
204
input                   iwb_ack_i;      // normal termination
205
input                   iwb_err_i;      // termination w/ error
206
input                   iwb_rty_i;      // termination w/ retry
207
input   [dw-1:0] iwb_dat_i;      // input data bus
208
output                  iwb_cyc_o;      // cycle valid output
209
output  [aw-1:0] iwb_adr_o;      // address bus outputs
210
output                  iwb_stb_o;      // strobe output
211
output                  iwb_we_o;       // indicates write transfer
212
output  [3:0]            iwb_sel_o;      // byte select outputs
213
output  [dw-1:0] iwb_dat_o;      // output data bus
214
`ifdef OR1200_WB_CAB
215
output                  iwb_cab_o;      // indicates consecutive address burst
216
`endif
217
`ifdef OR1200_WB_B3
218
output  [2:0]            iwb_cti_o;      // cycle type identifier
219
output  [1:0]            iwb_bte_o;      // burst type extension
220
`endif
221
 
222
//
223
// Data WISHBONE interface
224
//
225
input                   dwb_clk_i;      // clock input
226
input                   dwb_rst_i;      // reset input
227
input                   dwb_ack_i;      // normal termination
228
input                   dwb_err_i;      // termination w/ error
229
input                   dwb_rty_i;      // termination w/ retry
230
input   [dw-1:0] dwb_dat_i;      // input data bus
231
output                  dwb_cyc_o;      // cycle valid output
232
output  [aw-1:0] dwb_adr_o;      // address bus outputs
233
output                  dwb_stb_o;      // strobe output
234
output                  dwb_we_o;       // indicates write transfer
235
output  [3:0]            dwb_sel_o;      // byte select outputs
236
output  [dw-1:0] dwb_dat_o;      // output data bus
237
`ifdef OR1200_WB_CAB
238
output                  dwb_cab_o;      // indicates consecutive address burst
239
`endif
240
`ifdef OR1200_WB_B3
241
output  [2:0]            dwb_cti_o;      // cycle type identifier
242
output  [1:0]            dwb_bte_o;      // burst type extension
243
`endif
244
 
245
//
246
// External Debug Interface
247
//
248
input                   dbg_stall_i;    // External Stall Input
249
input                   dbg_ewt_i;      // External Watchpoint Trigger Input
250
output  [3:0]            dbg_lss_o;      // External Load/Store Unit Status
251
output  [1:0]            dbg_is_o;       // External Insn Fetch Status
252
output  [10:0]           dbg_wp_o;       // Watchpoints Outputs
253
output                  dbg_bp_o;       // Breakpoint Output
254
input                   dbg_stb_i;      // External Address/Data Strobe
255
input                   dbg_we_i;       // External Write Enable
256
input   [aw-1:0] dbg_adr_i;      // External Address Input
257
input   [dw-1:0] dbg_dat_i;      // External Data Input
258
output  [dw-1:0] dbg_dat_o;      // External Data Output
259
output                  dbg_ack_o;      // External Data Acknowledge (not WB compatible)
260
 
261
`ifdef OR1200_BIST
262
//
263
// RAM BIST
264
//
265
input mbist_si_i;
266
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
267
output mbist_so_o;
268
`endif
269
 
270
//
271
// Power Management
272
//
273
input                   pm_cpustall_i;
274
output  [3:0]            pm_clksd_o;
275
output                  pm_dc_gate_o;
276
output                  pm_ic_gate_o;
277
output                  pm_dmmu_gate_o;
278
output                  pm_immu_gate_o;
279
output                  pm_tt_gate_o;
280
output                  pm_cpu_gate_o;
281
output                  pm_wakeup_o;
282
output                  pm_lvolt_o;
283
 
284
 
285
//
286
// Internal wires and regs
287
//
288
 
289
//
290
// DC to SB
291
//
292
wire    [dw-1:0] dcsb_dat_dc;
293
wire    [aw-1:0] dcsb_adr_dc;
294
wire                    dcsb_cyc_dc;
295
wire                    dcsb_stb_dc;
296
wire                    dcsb_we_dc;
297
wire    [3:0]            dcsb_sel_dc;
298
wire                    dcsb_cab_dc;
299
wire    [dw-1:0] dcsb_dat_sb;
300
wire                    dcsb_ack_sb;
301
wire                    dcsb_err_sb;
302
 
303
//
304
// SB to BIU
305
//
306
wire    [dw-1:0] sbbiu_dat_sb;
307
wire    [aw-1:0] sbbiu_adr_sb;
308
wire                    sbbiu_cyc_sb;
309
wire                    sbbiu_stb_sb;
310
wire                    sbbiu_we_sb;
311
wire    [3:0]            sbbiu_sel_sb;
312
wire                    sbbiu_cab_sb;
313
wire    [dw-1:0] sbbiu_dat_biu;
314
wire                    sbbiu_ack_biu;
315
wire                    sbbiu_err_biu;
316
 
317
//
318
// IC to BIU
319
//
320
wire    [dw-1:0] icbiu_dat_ic;
321
wire    [aw-1:0] icbiu_adr_ic;
322
wire                    icbiu_cyc_ic;
323
wire                    icbiu_stb_ic;
324
wire                    icbiu_we_ic;
325
wire    [3:0]            icbiu_sel_ic;
326
wire    [3:0]            icbiu_tag_ic;
327
wire                    icbiu_cab_ic;
328
wire    [dw-1:0] icbiu_dat_biu;
329
wire                    icbiu_ack_biu;
330
wire                    icbiu_err_biu;
331
wire    [3:0]            icbiu_tag_biu;
332
 
333
//
334
// CPU's SPR access to various RISC units (shared wires)
335
//
336
wire                    supv;
337
wire    [aw-1:0] spr_addr;
338
wire    [dw-1:0] spr_dat_cpu;
339
wire    [31:0]           spr_cs;
340
wire                    spr_we;
341
 
342
//
343
// DMMU and CPU
344
//
345
wire                    dmmu_en;
346
wire    [31:0]           spr_dat_dmmu;
347
 
348
//
349
// DMMU and QMEM
350
//
351
wire                    qmemdmmu_err_qmem;
352
wire    [3:0]            qmemdmmu_tag_qmem;
353
wire    [aw-1:0] qmemdmmu_adr_dmmu;
354
wire                    qmemdmmu_cycstb_dmmu;
355
wire                    qmemdmmu_ci_dmmu;
356
 
357
//
358
// CPU and data memory subsystem
359
//
360
wire                    dc_en;
361
wire    [31:0]           dcpu_adr_cpu;
362
wire                    dcpu_cycstb_cpu;
363
wire                    dcpu_we_cpu;
364
wire    [3:0]            dcpu_sel_cpu;
365
wire    [3:0]            dcpu_tag_cpu;
366
wire    [31:0]           dcpu_dat_cpu;
367
wire    [31:0]           dcpu_dat_qmem;
368
wire                    dcpu_ack_qmem;
369
wire                    dcpu_rty_qmem;
370
wire                    dcpu_err_dmmu;
371
wire    [3:0]            dcpu_tag_dmmu;
372
 
373
//
374
// IMMU and CPU
375
//
376
wire                    immu_en;
377
wire    [31:0]           spr_dat_immu;
378
 
379
//
380
// CPU and insn memory subsystem
381
//
382
wire                    ic_en;
383
wire    [31:0]           icpu_adr_cpu;
384
wire                    icpu_cycstb_cpu;
385
wire    [3:0]            icpu_sel_cpu;
386
wire    [3:0]            icpu_tag_cpu;
387
wire    [31:0]           icpu_dat_qmem;
388
wire                    icpu_ack_qmem;
389
wire    [31:0]           icpu_adr_immu;
390
wire                    icpu_err_immu;
391
wire    [3:0]            icpu_tag_immu;
392
wire                    icpu_rty_immu;
393
 
394
//
395
// IMMU and QMEM
396
//
397
wire    [aw-1:0] qmemimmu_adr_immu;
398
wire                    qmemimmu_rty_qmem;
399
wire                    qmemimmu_err_qmem;
400
wire    [3:0]            qmemimmu_tag_qmem;
401
wire                    qmemimmu_cycstb_immu;
402
wire                    qmemimmu_ci_immu;
403
 
404
//
405
// QMEM and IC
406
//
407
wire    [aw-1:0] icqmem_adr_qmem;
408
wire                    icqmem_rty_ic;
409
wire                    icqmem_err_ic;
410
wire    [3:0]            icqmem_tag_ic;
411
wire                    icqmem_cycstb_qmem;
412
wire                    icqmem_ci_qmem;
413
wire    [31:0]           icqmem_dat_ic;
414
wire                    icqmem_ack_ic;
415
 
416
//
417
// QMEM and DC
418
//
419
wire    [aw-1:0] dcqmem_adr_qmem;
420
wire                    dcqmem_rty_dc;
421
wire                    dcqmem_err_dc;
422
wire    [3:0]            dcqmem_tag_dc;
423
wire                    dcqmem_cycstb_qmem;
424
wire                    dcqmem_ci_qmem;
425
wire    [31:0]           dcqmem_dat_dc;
426
wire    [31:0]           dcqmem_dat_qmem;
427
wire                    dcqmem_we_qmem;
428
wire    [3:0]            dcqmem_sel_qmem;
429
wire                    dcqmem_ack_dc;
430
 
431
//
432
// Connection between CPU and PIC
433
//
434
wire    [dw-1:0] spr_dat_pic;
435
wire                    pic_wakeup;
436
wire                    sig_int;
437
 
438
//
439
// Connection between CPU and PM
440
//
441
wire    [dw-1:0] spr_dat_pm;
442
 
443
//
444
// CPU and TT
445
//
446
wire    [dw-1:0] spr_dat_tt;
447
wire                    sig_tick;
448
 
449
//
450
// Debug port and caches/MMUs
451
//
452
wire    [dw-1:0] spr_dat_du;
453
wire                    du_stall;
454
wire    [dw-1:0] du_addr;
455
wire    [dw-1:0] du_dat_du;
456
wire                    du_read;
457
wire                    du_write;
458
wire    [12:0]           du_except;
459
wire    [`OR1200_DU_DSR_WIDTH-1:0]     du_dsr;
460
wire    [dw-1:0] du_dat_cpu;
461
wire                    du_hwbkpt;
462
 
463
wire                    ex_freeze;
464
wire    [31:0]           ex_insn;
465
wire    [31:0]           id_pc;
466
wire    [`OR1200_BRANCHOP_WIDTH-1:0]     branch_op;
467
wire    [31:0]           spr_dat_npc;
468
wire    [31:0]           rf_dataw;
469
 
470
`ifdef OR1200_BIST
471
//
472
// RAM BIST
473
//
474
wire                    mbist_immu_so;
475
wire                    mbist_ic_so;
476
wire                    mbist_dmmu_so;
477
wire                    mbist_dc_so;
478
wire      mbist_qmem_so;
479
wire                    mbist_immu_si = mbist_si_i;
480
wire                    mbist_ic_si = mbist_immu_so;
481
wire                    mbist_qmem_si = mbist_ic_so;
482
wire                    mbist_dmmu_si = mbist_qmem_so;
483
wire                    mbist_dc_si = mbist_dmmu_so;
484
assign                  mbist_so_o = mbist_dc_so;
485
`endif
486
 
487
wire  [3:0] icqmem_sel_qmem;
488
wire  [3:0] icqmem_tag_qmem;
489
wire  [3:0] dcqmem_tag_qmem;
490
 
491
//
492
// Instantiation of Instruction WISHBONE BIU
493
//
494
or1200_iwb_biu iwb_biu(
495
        // RISC clk, rst and clock control
496
        .clk(clk_i),
497
        .rst(rst_i),
498
        .clmode(clmode_i),
499
 
500
        // WISHBONE interface
501
        .wb_clk_i(iwb_clk_i),
502
        .wb_rst_i(iwb_rst_i),
503
        .wb_ack_i(iwb_ack_i),
504
        .wb_err_i(iwb_err_i),
505
        .wb_rty_i(iwb_rty_i),
506
        .wb_dat_i(iwb_dat_i),
507
        .wb_cyc_o(iwb_cyc_o),
508
        .wb_adr_o(iwb_adr_o),
509
        .wb_stb_o(iwb_stb_o),
510
        .wb_we_o(iwb_we_o),
511
        .wb_sel_o(iwb_sel_o),
512
        .wb_dat_o(iwb_dat_o),
513
`ifdef OR1200_WB_CAB
514
        .wb_cab_o(iwb_cab_o),
515
`endif
516
`ifdef OR1200_WB_B3
517
        .wb_cti_o(iwb_cti_o),
518
        .wb_bte_o(iwb_bte_o),
519
`endif
520
 
521
        // Internal RISC bus
522
        .biu_dat_i(icbiu_dat_ic),
523
        .biu_adr_i(icbiu_adr_ic),
524
        .biu_cyc_i(icbiu_cyc_ic),
525
        .biu_stb_i(icbiu_stb_ic),
526
        .biu_we_i(icbiu_we_ic),
527
        .biu_sel_i(icbiu_sel_ic),
528
        .biu_cab_i(icbiu_cab_ic),
529
        .biu_dat_o(icbiu_dat_biu),
530
        .biu_ack_o(icbiu_ack_biu),
531
        .biu_err_o(icbiu_err_biu)
532
);
533
 
534
//
535
// Instantiation of Data WISHBONE BIU
536
//
537
or1200_wb_biu dwb_biu(
538
        // RISC clk, rst and clock control
539
        .clk(clk_i),
540
        .rst(rst_i),
541
        .clmode(clmode_i),
542
 
543
        // WISHBONE interface
544
        .wb_clk_i(dwb_clk_i),
545
        .wb_rst_i(dwb_rst_i),
546
        .wb_ack_i(dwb_ack_i),
547
        .wb_err_i(dwb_err_i),
548
        .wb_rty_i(dwb_rty_i),
549
        .wb_dat_i(dwb_dat_i),
550
        .wb_cyc_o(dwb_cyc_o),
551
        .wb_adr_o(dwb_adr_o),
552
        .wb_stb_o(dwb_stb_o),
553
        .wb_we_o(dwb_we_o),
554
        .wb_sel_o(dwb_sel_o),
555
        .wb_dat_o(dwb_dat_o),
556
`ifdef OR1200_WB_CAB
557
        .wb_cab_o(dwb_cab_o),
558
`endif
559
`ifdef OR1200_WB_B3
560
        .wb_cti_o(dwb_cti_o),
561
        .wb_bte_o(dwb_bte_o),
562
`endif
563
 
564
        // Internal RISC bus
565
        .biu_dat_i(sbbiu_dat_sb),
566
        .biu_adr_i(sbbiu_adr_sb),
567
        .biu_cyc_i(sbbiu_cyc_sb),
568
        .biu_stb_i(sbbiu_stb_sb),
569
        .biu_we_i(sbbiu_we_sb),
570
        .biu_sel_i(sbbiu_sel_sb),
571
        .biu_cab_i(sbbiu_cab_sb),
572
        .biu_dat_o(sbbiu_dat_biu),
573
        .biu_ack_o(sbbiu_ack_biu),
574
        .biu_err_o(sbbiu_err_biu)
575
);
576
 
577
//
578
// Instantiation of IMMU
579
//
580
or1200_immu_top or1200_immu_top(
581
        // Rst and clk
582
        .clk(clk_i),
583
        .rst(rst_i),
584
 
585
`ifdef OR1200_BIST
586
        // RAM BIST
587
        .mbist_si_i(mbist_immu_si),
588
        .mbist_so_o(mbist_immu_so),
589
        .mbist_ctrl_i(mbist_ctrl_i),
590
`endif
591
 
592
        // CPU and IMMU
593
        .ic_en(ic_en),
594
        .immu_en(immu_en),
595
        .supv(supv),
596
        .icpu_adr_i(icpu_adr_cpu),
597
        .icpu_cycstb_i(icpu_cycstb_cpu),
598
        .icpu_adr_o(icpu_adr_immu),
599
        .icpu_tag_o(icpu_tag_immu),
600
        .icpu_rty_o(icpu_rty_immu),
601
        .icpu_err_o(icpu_err_immu),
602
 
603
        // SPR access
604
        .spr_cs(spr_cs[`OR1200_SPR_GROUP_IMMU]),
605
        .spr_write(spr_we),
606
        .spr_addr(spr_addr),
607
        .spr_dat_i(spr_dat_cpu),
608
        .spr_dat_o(spr_dat_immu),
609
 
610
        // QMEM and IMMU
611
        .qmemimmu_rty_i(qmemimmu_rty_qmem),
612
        .qmemimmu_err_i(qmemimmu_err_qmem),
613
        .qmemimmu_tag_i(qmemimmu_tag_qmem),
614
        .qmemimmu_adr_o(qmemimmu_adr_immu),
615
        .qmemimmu_cycstb_o(qmemimmu_cycstb_immu),
616
        .qmemimmu_ci_o(qmemimmu_ci_immu)
617
);
618
 
619
//
620
// Instantiation of Instruction Cache
621
//
622
or1200_ic_top or1200_ic_top(
623
        .clk(clk_i),
624
        .rst(rst_i),
625
 
626
`ifdef OR1200_BIST
627
        // RAM BIST
628
        .mbist_si_i(mbist_ic_si),
629
        .mbist_so_o(mbist_ic_so),
630
        .mbist_ctrl_i(mbist_ctrl_i),
631
`endif
632
 
633
        // IC and QMEM
634
        .ic_en(ic_en),
635
        .icqmem_adr_i(icqmem_adr_qmem),
636
        .icqmem_cycstb_i(icqmem_cycstb_qmem),
637
        .icqmem_ci_i(icqmem_ci_qmem),
638
        .icqmem_sel_i(icqmem_sel_qmem),
639
        .icqmem_tag_i(icqmem_tag_qmem),
640
        .icqmem_dat_o(icqmem_dat_ic),
641
        .icqmem_ack_o(icqmem_ack_ic),
642
        .icqmem_rty_o(icqmem_rty_ic),
643
        .icqmem_err_o(icqmem_err_ic),
644
        .icqmem_tag_o(icqmem_tag_ic),
645
 
646
        // SPR access
647
        .spr_cs(spr_cs[`OR1200_SPR_GROUP_IC]),
648
        .spr_write(spr_we),
649
        .spr_dat_i(spr_dat_cpu),
650
 
651
        // IC and BIU
652
        .icbiu_dat_o(icbiu_dat_ic),
653
        .icbiu_adr_o(icbiu_adr_ic),
654
        .icbiu_cyc_o(icbiu_cyc_ic),
655
        .icbiu_stb_o(icbiu_stb_ic),
656
        .icbiu_we_o(icbiu_we_ic),
657
        .icbiu_sel_o(icbiu_sel_ic),
658
        .icbiu_cab_o(icbiu_cab_ic),
659
        .icbiu_dat_i(icbiu_dat_biu),
660
        .icbiu_ack_i(icbiu_ack_biu),
661
        .icbiu_err_i(icbiu_err_biu)
662
);
663
 
664
//
665
// Instantiation of CPU                 // change by bviyer
666
//
667
or1200_cpu or1200_cpu(
668
        .clk(clk_i),
669
        .rst(rst_i),
670
 
671
        // Connection QMEM and IFETCHER inside CPU
672
        .ic_en(ic_en),
673
        .icpu_adr_o(icpu_adr_cpu),
674
        .icpu_cycstb_o(icpu_cycstb_cpu),
675
        .icpu_sel_o(icpu_sel_cpu),
676
        .icpu_tag_o(icpu_tag_cpu),
677
        .icpu_dat_i(icpu_dat_qmem),
678
        .icpu_ack_i(icpu_ack_qmem),
679
        .icpu_rty_i(icpu_rty_immu),
680
        .icpu_adr_i(icpu_adr_immu),
681
        .icpu_err_i(icpu_err_immu),
682
        .icpu_tag_i(icpu_tag_immu),
683
 
684
        // Connection CPU to external Debug port
685
        .ex_freeze(ex_freeze),
686
        .ex_insn(ex_insn),
687
        .id_pc(id_pc),
688
        .branch_op(branch_op),
689
        .du_stall(du_stall),
690
        .du_addr(du_addr),
691
        .du_dat_du(du_dat_du),
692
        .du_read(du_read),
693
        .du_write(du_write),
694
        .du_dsr(du_dsr),
695
        .du_except(du_except),
696
        .du_dat_cpu(du_dat_cpu),
697
        .du_hwbkpt(du_hwbkpt),
698
        .rf_dataw(rf_dataw),
699
 
700
 
701
        // Connection IMMU and CPU internally
702
        .immu_en(immu_en),
703
 
704
        // Connection QMEM and CPU
705
        .dc_en(dc_en),
706
        .dcpu_adr_o(dcpu_adr_cpu),
707
        .dcpu_cycstb_o(dcpu_cycstb_cpu),
708
        .dcpu_we_o(dcpu_we_cpu),
709
        .dcpu_sel_o(dcpu_sel_cpu),
710
        .dcpu_tag_o(dcpu_tag_cpu),
711
        .dcpu_dat_o(dcpu_dat_cpu),
712
        .dcpu_dat_i(dcpu_dat_qmem),
713
        .dcpu_ack_i(dcpu_ack_qmem),
714
        .dcpu_rty_i(dcpu_rty_qmem),
715
        .dcpu_err_i(dcpu_err_dmmu),
716
        .dcpu_tag_i(dcpu_tag_dmmu),
717
 
718
        // Connection DMMU and CPU internally
719
        .dmmu_en(dmmu_en),
720
 
721
        // Connection PIC and CPU's EXCEPT
722
        .sig_int(sig_int),
723
        .sig_tick(sig_tick),
724
 
725
        // SPRs
726
        .supv(supv),
727
        .spr_addr(spr_addr),
728
        .spr_dat_cpu(spr_dat_cpu),
729
        .spr_dat_pic(spr_dat_pic),
730
        .spr_dat_tt(spr_dat_tt),
731
        .spr_dat_pm(spr_dat_pm),
732
        .spr_dat_dmmu(spr_dat_dmmu),
733
        .spr_dat_immu(spr_dat_immu),
734
        .spr_dat_du(spr_dat_du),
735
        .spr_dat_npc(spr_dat_npc),
736
        .spr_cs(spr_cs),
737
        .spr_we(spr_we)
738
);
739
 
740
//
741
// Instantiation of DMMU
742
//
743
or1200_dmmu_top or1200_dmmu_top(
744
        // Rst and clk
745
        .clk(clk_i),
746
        .rst(rst_i),
747
 
748
`ifdef OR1200_BIST
749
        // RAM BIST
750
        .mbist_si_i(mbist_dmmu_si),
751
        .mbist_so_o(mbist_dmmu_so),
752
        .mbist_ctrl_i(mbist_ctrl_i),
753
`endif
754
 
755
        // CPU i/f
756
        .dc_en(dc_en),
757
        .dmmu_en(dmmu_en),
758
        .supv(supv),
759
        .dcpu_adr_i(dcpu_adr_cpu),
760
        .dcpu_cycstb_i(dcpu_cycstb_cpu),
761
        .dcpu_we_i(dcpu_we_cpu),
762
        .dcpu_tag_o(dcpu_tag_dmmu),
763
        .dcpu_err_o(dcpu_err_dmmu),
764
 
765
        // SPR access
766
        .spr_cs(spr_cs[`OR1200_SPR_GROUP_DMMU]),
767
        .spr_write(spr_we),
768
        .spr_addr(spr_addr),
769
        .spr_dat_i(spr_dat_cpu),
770
        .spr_dat_o(spr_dat_dmmu),
771
 
772
        // QMEM and DMMU
773
        .qmemdmmu_err_i(qmemdmmu_err_qmem),
774
        .qmemdmmu_tag_i(qmemdmmu_tag_qmem),
775
        .qmemdmmu_adr_o(qmemdmmu_adr_dmmu),
776
        .qmemdmmu_cycstb_o(qmemdmmu_cycstb_dmmu),
777
        .qmemdmmu_ci_o(qmemdmmu_ci_dmmu)
778
);
779
 
780
//
781
// Instantiation of Data Cache
782
//
783
or1200_dc_top or1200_dc_top(
784
        .clk(clk_i),
785
        .rst(rst_i),
786
 
787
`ifdef OR1200_BIST
788
        // RAM BIST
789
        .mbist_si_i(mbist_dc_si),
790
        .mbist_so_o(mbist_dc_so),
791
        .mbist_ctrl_i(mbist_ctrl_i),
792
`endif
793
 
794
        // DC and QMEM
795
        .dc_en(dc_en),
796
        .dcqmem_adr_i(dcqmem_adr_qmem),
797
        .dcqmem_cycstb_i(dcqmem_cycstb_qmem),
798
        .dcqmem_ci_i(dcqmem_ci_qmem),
799
        .dcqmem_we_i(dcqmem_we_qmem),
800
        .dcqmem_sel_i(dcqmem_sel_qmem),
801
        .dcqmem_tag_i(dcqmem_tag_qmem),
802
        .dcqmem_dat_i(dcqmem_dat_qmem),
803
        .dcqmem_dat_o(dcqmem_dat_dc),
804
        .dcqmem_ack_o(dcqmem_ack_dc),
805
        .dcqmem_rty_o(dcqmem_rty_dc),
806
        .dcqmem_err_o(dcqmem_err_dc),
807
        .dcqmem_tag_o(dcqmem_tag_dc),
808
 
809
        // SPR access
810
        .spr_cs(spr_cs[`OR1200_SPR_GROUP_DC]),
811
        .spr_write(spr_we),
812
        .spr_dat_i(spr_dat_cpu),
813
 
814
        // DC and BIU
815
        .dcsb_dat_o(dcsb_dat_dc),
816
        .dcsb_adr_o(dcsb_adr_dc),
817
        .dcsb_cyc_o(dcsb_cyc_dc),
818
        .dcsb_stb_o(dcsb_stb_dc),
819
        .dcsb_we_o(dcsb_we_dc),
820
        .dcsb_sel_o(dcsb_sel_dc),
821
        .dcsb_cab_o(dcsb_cab_dc),
822
        .dcsb_dat_i(dcsb_dat_sb),
823
        .dcsb_ack_i(dcsb_ack_sb),
824
        .dcsb_err_i(dcsb_err_sb)
825
);
826
 
827
//
828
// Instantiation of embedded memory - qmem
829
//
830
or1200_qmem_top or1200_qmem_top(
831
        .clk(clk_i),
832
        .rst(rst_i),
833
 
834
`ifdef OR1200_BIST
835
        // RAM BIST
836
        .mbist_si_i(mbist_qmem_si),
837
        .mbist_so_o(mbist_qmem_so),
838
        .mbist_ctrl_i(mbist_ctrl_i),
839
`endif
840
 
841
        // QMEM and CPU/IMMU
842
        .qmemimmu_adr_i(qmemimmu_adr_immu),
843
        .qmemimmu_cycstb_i(qmemimmu_cycstb_immu),
844
        .qmemimmu_ci_i(qmemimmu_ci_immu),
845
        .qmemicpu_sel_i(icpu_sel_cpu),
846
        .qmemicpu_tag_i(icpu_tag_cpu),
847
        .qmemicpu_dat_o(icpu_dat_qmem),
848
        .qmemicpu_ack_o(icpu_ack_qmem),
849
        .qmemimmu_rty_o(qmemimmu_rty_qmem),
850
        .qmemimmu_err_o(qmemimmu_err_qmem),
851
        .qmemimmu_tag_o(qmemimmu_tag_qmem),
852
 
853
        // QMEM and IC
854
        .icqmem_adr_o(icqmem_adr_qmem),
855
        .icqmem_cycstb_o(icqmem_cycstb_qmem),
856
        .icqmem_ci_o(icqmem_ci_qmem),
857
        .icqmem_sel_o(icqmem_sel_qmem),
858
        .icqmem_tag_o(icqmem_tag_qmem),
859
        .icqmem_dat_i(icqmem_dat_ic),
860
        .icqmem_ack_i(icqmem_ack_ic),
861
        .icqmem_rty_i(icqmem_rty_ic),
862
        .icqmem_err_i(icqmem_err_ic),
863
        .icqmem_tag_i(icqmem_tag_ic),
864
 
865
        // QMEM and CPU/DMMU
866
        .qmemdmmu_adr_i(qmemdmmu_adr_dmmu),
867
        .qmemdmmu_cycstb_i(qmemdmmu_cycstb_dmmu),
868
        .qmemdmmu_ci_i(qmemdmmu_ci_dmmu),
869
        .qmemdcpu_we_i(dcpu_we_cpu),
870
        .qmemdcpu_sel_i(dcpu_sel_cpu),
871
        .qmemdcpu_tag_i(dcpu_tag_cpu),
872
        .qmemdcpu_dat_i(dcpu_dat_cpu),
873
        .qmemdcpu_dat_o(dcpu_dat_qmem),
874
        .qmemdcpu_ack_o(dcpu_ack_qmem),
875
        .qmemdcpu_rty_o(dcpu_rty_qmem),
876
        .qmemdmmu_err_o(qmemdmmu_err_qmem),
877
        .qmemdmmu_tag_o(qmemdmmu_tag_qmem),
878
 
879
        // QMEM and DC
880
        .dcqmem_adr_o(dcqmem_adr_qmem),
881
        .dcqmem_cycstb_o(dcqmem_cycstb_qmem),
882
        .dcqmem_ci_o(dcqmem_ci_qmem),
883
        .dcqmem_we_o(dcqmem_we_qmem),
884
        .dcqmem_sel_o(dcqmem_sel_qmem),
885
        .dcqmem_tag_o(dcqmem_tag_qmem),
886
        .dcqmem_dat_o(dcqmem_dat_qmem),
887
        .dcqmem_dat_i(dcqmem_dat_dc),
888
        .dcqmem_ack_i(dcqmem_ack_dc),
889
        .dcqmem_rty_i(dcqmem_rty_dc),
890
        .dcqmem_err_i(dcqmem_err_dc),
891
        .dcqmem_tag_i(dcqmem_tag_dc)
892
);
893
 
894
//
895
// Instantiation of Store Buffer
896
//
897
or1200_sb or1200_sb(
898
        // RISC clock, reset
899
        .clk(clk_i),
900
        .rst(rst_i),
901
 
902
        // Internal RISC bus (DC<->SB)
903
        .dcsb_dat_i(dcsb_dat_dc),
904
        .dcsb_adr_i(dcsb_adr_dc),
905
        .dcsb_cyc_i(dcsb_cyc_dc),
906
        .dcsb_stb_i(dcsb_stb_dc),
907
        .dcsb_we_i(dcsb_we_dc),
908
        .dcsb_sel_i(dcsb_sel_dc),
909
        .dcsb_cab_i(dcsb_cab_dc),
910
        .dcsb_dat_o(dcsb_dat_sb),
911
        .dcsb_ack_o(dcsb_ack_sb),
912
        .dcsb_err_o(dcsb_err_sb),
913
 
914
        // SB and BIU
915
        .sbbiu_dat_o(sbbiu_dat_sb),
916
        .sbbiu_adr_o(sbbiu_adr_sb),
917
        .sbbiu_cyc_o(sbbiu_cyc_sb),
918
        .sbbiu_stb_o(sbbiu_stb_sb),
919
        .sbbiu_we_o(sbbiu_we_sb),
920
        .sbbiu_sel_o(sbbiu_sel_sb),
921
        .sbbiu_cab_o(sbbiu_cab_sb),
922
        .sbbiu_dat_i(sbbiu_dat_biu),
923
        .sbbiu_ack_i(sbbiu_ack_biu),
924
        .sbbiu_err_i(sbbiu_err_biu)
925
);
926
 
927
//
928
// Instantiation of Debug Unit
929
//
930
or1200_du or1200_du(
931
        // RISC Internal Interface
932
        .clk(clk_i),
933
        .rst(rst_i),
934
        .dcpu_cycstb_i(dcpu_cycstb_cpu),
935
        .dcpu_we_i(dcpu_we_cpu),
936
        .dcpu_adr_i(dcpu_adr_cpu),
937
        .dcpu_dat_lsu(dcpu_dat_cpu),
938
        .dcpu_dat_dc(dcpu_dat_qmem),
939
        .icpu_cycstb_i(icpu_cycstb_cpu),
940
        .ex_freeze(ex_freeze),
941
        .branch_op(branch_op),
942
        .ex_insn(ex_insn),
943
        .id_pc(id_pc),
944
        .du_dsr(du_dsr),
945
 
946
        // For Trace buffer
947
        .spr_dat_npc(spr_dat_npc),
948
        .rf_dataw(rf_dataw),
949
 
950
        // DU's access to SPR unit
951
        .du_stall(du_stall),
952
        .du_addr(du_addr),
953
        .du_dat_i(du_dat_cpu),
954
        .du_dat_o(du_dat_du),
955
        .du_read(du_read),
956
        .du_write(du_write),
957
        .du_except(du_except),
958
        .du_hwbkpt(du_hwbkpt),
959
 
960
        // Access to DU's SPRs
961
        .spr_cs(spr_cs[`OR1200_SPR_GROUP_DU]),
962
        .spr_write(spr_we),
963
        .spr_addr(spr_addr),
964
        .spr_dat_i(spr_dat_cpu),
965
        .spr_dat_o(spr_dat_du),
966
 
967
        // External Debug Interface
968
        .dbg_stall_i(dbg_stall_i),
969
        .dbg_ewt_i(dbg_ewt_i),
970
        .dbg_lss_o(dbg_lss_o),
971
        .dbg_is_o(dbg_is_o),
972
        .dbg_wp_o(dbg_wp_o),
973
        .dbg_bp_o(dbg_bp_o),
974
        .dbg_stb_i(dbg_stb_i),
975
        .dbg_we_i(dbg_we_i),
976
        .dbg_adr_i(dbg_adr_i),
977
        .dbg_dat_i(dbg_dat_i),
978
        .dbg_dat_o(dbg_dat_o),
979
        .dbg_ack_o(dbg_ack_o)
980
);
981
 
982
//
983
// Programmable interrupt controller
984
//
985
or1200_pic or1200_pic(
986
        // RISC Internal Interface
987
        .clk(clk_i),
988
        .rst(rst_i),
989
        .spr_cs(spr_cs[`OR1200_SPR_GROUP_PIC]),
990
        .spr_write(spr_we),
991
        .spr_addr(spr_addr),
992
        .spr_dat_i(spr_dat_cpu),
993
        .spr_dat_o(spr_dat_pic),
994
        .pic_wakeup(pic_wakeup),
995
        .int(sig_int),
996
 
997
        // PIC Interface
998
        .pic_int(pic_ints_i)
999
);
1000
 
1001
//
1002
// Instantiation of Tick timer
1003
//
1004
or1200_tt or1200_tt(
1005
        // RISC Internal Interface
1006
        .clk(clk_i),
1007
        .rst(rst_i),
1008
        .du_stall(du_stall),
1009
        .spr_cs(spr_cs[`OR1200_SPR_GROUP_TT]),
1010
        .spr_write(spr_we),
1011
        .spr_addr(spr_addr),
1012
        .spr_dat_i(spr_dat_cpu),
1013
        .spr_dat_o(spr_dat_tt),
1014
        .int(sig_tick)
1015
);
1016
 
1017
//
1018
// Instantiation of Power Management
1019
//
1020
or1200_pm or1200_pm(
1021
        // RISC Internal Interface
1022
        .clk(clk_i),
1023
        .rst(rst_i),
1024
        .pic_wakeup(pic_wakeup),
1025
        .spr_write(spr_we),
1026
        .spr_addr(spr_addr),
1027
        .spr_dat_i(spr_dat_cpu),
1028
        .spr_dat_o(spr_dat_pm),
1029
 
1030
        // Power Management Interface
1031
        .pm_cpustall(pm_cpustall_i),
1032
        .pm_clksd(pm_clksd_o),
1033
        .pm_dc_gate(pm_dc_gate_o),
1034
        .pm_ic_gate(pm_ic_gate_o),
1035
        .pm_dmmu_gate(pm_dmmu_gate_o),
1036
        .pm_immu_gate(pm_immu_gate_o),
1037
        .pm_tt_gate(pm_tt_gate_o),
1038
        .pm_cpu_gate(pm_cpu_gate_o),
1039
        .pm_wakeup(pm_wakeup_o),
1040
        .pm_lvolt(pm_lvolt_o)
1041
);
1042
 
1043
 
1044
endmodule

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