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[/] [claw/] [trunk/] [or1200_cpu/] [or1200_tpram_32x32.v] - Blame information for rev 4

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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  Generic Two-Port Synchronous RAM                            ////
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////                                                              ////
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////  This file is part of memory library available from          ////
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////  http://www.opencores.org/cvsweb.shtml/generic_memories/     ////
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////                                                              ////
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////  Description                                                 ////
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////  This block is a wrapper with common two-port                ////
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////  synchronous memory interface for different                  ////
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////  types of ASIC and FPGA RAMs. Beside universal memory        ////
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////  interface it also provides behavioral model of generic      ////
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////  two-port synchronous RAM.                                   ////
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////  It should be used in all OPENCORES designs that want to be  ////
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////  portable accross different target technologies and          ////
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////  independent of target memory.                               ////
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////                                                              ////
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////  Supported ASIC RAMs are:                                    ////
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////  - Artisan Double-Port Sync RAM                              ////
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////  - Avant! Two-Port Sync RAM (*)                              ////
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////  - Virage 2-port Sync RAM                                    ////
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////                                                              ////
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////  Supported FPGA RAMs are:                                    ////
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////  - Xilinx Virtex RAMB4_S16_S16                               ////
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////  - Altera LPM                                                ////
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////                                                              ////
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////  To Do:                                                      ////
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////   - fix Avant!                                               ////
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////   - xilinx rams need external tri-state logic                ////
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////   - add additional RAMs (VS etc)                             ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Damjan Lampret, lampret@opencores.org                 ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
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// Revision 1.3  2004/04/05 08:29:57  lampret
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// Merged branch_qmem into main tree.
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//
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// Revision 1.2.4.1  2003/07/08 15:36:37  lampret
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// Added embedded memory QMEM.
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//
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// Revision 1.2  2003/04/07 01:19:07  lampret
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// Added Altera LPM RAMs. Changed generic RAM output when OE inactive.
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//
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// Revision 1.1  2002/01/03 08:16:15  lampret
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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//
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// Revision 1.7  2001/10/21 17:57:16  lampret
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// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
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//
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// Revision 1.6  2001/10/14 13:12:09  lampret
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// MP3 version.
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//
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// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
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// no message
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//
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// Revision 1.1  2001/08/09 13:39:33  lampret
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// Major clean-up.
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//
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// Revision 1.2  2001/07/30 05:38:02  lampret
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// Adding empty directories required by HDL coding guidelines
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//
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//
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// synopsys translate_off
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`include "timescale.v"
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// synopsys translate_on
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`include "or1200_defines.v"
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99
module or1200_tpram_32x32(
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        // Generic synchronous two-port RAM interface
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        clk_a, rst_a, ce_a, we_a, oe_a, addr_a, di_a, do_a,
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        clk_b, rst_b, ce_b, we_b, oe_b, addr_b, di_b, do_b
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);
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105
//
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// Default address and data buses width
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//
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parameter aw = 5;
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parameter dw = 32;
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111
//
112
// Generic synchronous two-port RAM interface
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//
114
input                   clk_a;  // Clock
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input                   rst_a;  // Reset
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input                   ce_a;   // Chip enable input
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input                   we_a;   // Write enable input
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input                   oe_a;   // Output enable input
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input   [aw-1:0] addr_a; // address bus inputs
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input   [dw-1:0] di_a;   // input data bus
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output  [dw-1:0] do_a;   // output data bus
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input                   clk_b;  // Clock
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input                   rst_b;  // Reset
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input                   ce_b;   // Chip enable input
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input                   we_b;   // Write enable input
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input                   oe_b;   // Output enable input
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input   [aw-1:0] addr_b; // address bus inputs
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input   [dw-1:0] di_b;   // input data bus
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output  [dw-1:0] do_b;   // output data bus
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131
//
132
// Internal wires and registers
133
//
134
 
135
 
136
`ifdef OR1200_ARTISAN_SDP
137
 
138
//
139
// Instantiation of ASIC memory:
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//
141
// Artisan Synchronous Double-Port RAM (ra2sh)
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//
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`ifdef UNUSED
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art_hsdp_32x32 #(dw, 1<<aw, aw) artisan_sdp(
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`else
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art_hsdp_32x32 artisan_sdp(
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`endif
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        .qa(do_a),
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        .clka(clk_a),
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        .cena(~ce_a),
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        .wena(~we_a),
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        .aa(addr_a),
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        .da(di_a),
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        .oena(~oe_a),
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        .qb(do_b),
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        .clkb(clk_b),
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        .cenb(~ce_b),
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        .wenb(~we_b),
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        .ab(addr_b),
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        .db(di_b),
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        .oenb(~oe_b)
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);
163
 
164
`else
165
 
166
`ifdef OR1200_AVANT_ATP
167
 
168
//
169
// Instantiation of ASIC memory:
170
//
171
// Avant! Asynchronous Two-Port RAM
172
//
173
avant_atp avant_atp(
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        .web(~we),
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        .reb(),
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        .oeb(~oe),
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        .rcsb(),
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        .wcsb(),
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        .ra(addr),
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        .wa(addr),
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        .di(di),
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        .do(do)
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);
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185
`else
186
 
187
`ifdef OR1200_VIRAGE_STP
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//
190
// Instantiation of ASIC memory:
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//
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// Virage Synchronous 2-port R/W RAM
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//
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virage_stp virage_stp(
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        .QA(do_a),
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        .QB(do_b),
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        .ADRA(addr_a),
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        .DA(di_a),
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        .WEA(we_a),
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        .OEA(oe_a),
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        .MEA(ce_a),
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        .CLKA(clk_a),
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        .ADRB(adr_b),
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        .DB(di_b),
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        .WEB(we_b),
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        .OEB(oe_b),
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        .MEB(ce_b),
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        .CLKB(clk_b)
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);
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213
`else
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`ifdef OR1200_XILINX_RAMB4
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//
218
// Instantiation of FPGA memory:
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//
220
// Virtex/Spartan2
221
//
222
 
223
//
224
// Block 0
225
//
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RAMB4_S16_S16 ramb4_s16_s16_0(
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        .CLKA(clk_a),
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        .RSTA(rst_a),
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        .ADDRA(addr_a),
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        .DIA(di_a[15:0]),
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        .ENA(ce_a),
232
        .WEA(we_a),
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        .DOA(do_a[15:0]),
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        .CLKB(clk_b),
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        .RSTB(rst_b),
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        .ADDRB(addr_b),
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        .DIB(di_b[15:0]),
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        .ENB(ce_b),
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        .WEB(we_b),
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        .DOB(do_b[15:0])
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);
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//
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// Block 1
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//
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RAMB4_S16_S16 ramb4_s16_s16_1(
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        .CLKA(clk_a),
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        .RSTA(rst_a),
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        .ADDRA(addr_a),
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        .DIA(di_a[31:16]),
252
        .ENA(ce_a),
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        .WEA(we_a),
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        .DOA(do_a[31:16]),
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        .CLKB(clk_b),
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        .RSTB(rst_b),
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        .ADDRB(addr_b),
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        .DIB(di_b[31:16]),
260
        .ENB(ce_b),
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        .WEB(we_b),
262
        .DOB(do_b[31:16])
263
);
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265
`else
266
 
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`ifdef OR1200_ALTERA_LPM_XXX
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//
270
// Instantiation of FPGA memory:
271
//
272
// Altera LPM
273
//
274
// Added By Jamil Khatib
275
//
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altqpram altqpram_component (
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        .wraddress_a (addr_a),
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        .inclocken_a (ce_a),
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        .wraddress_b (addr_b),
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        .wren_a (we_a),
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        .inclocken_b (ce_b),
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        .wren_b (we_b),
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        .inaclr_a (rst_a),
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        .inaclr_b (rst_b),
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        .inclock_a (clk_a),
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        .inclock_b (clk_b),
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        .data_a (di_a),
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        .data_b (di_b),
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        .q_a (do_a),
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        .q_b (do_b)
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);
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293
defparam altqpram_component.operation_mode = "BIDIR_DUAL_PORT",
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        altqpram_component.width_write_a = dw,
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        altqpram_component.widthad_write_a = aw,
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        altqpram_component.numwords_write_a = dw,
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        altqpram_component.width_read_a = dw,
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        altqpram_component.widthad_read_a = aw,
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        altqpram_component.numwords_read_a = dw,
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        altqpram_component.width_write_b = dw,
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        altqpram_component.widthad_write_b = aw,
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        altqpram_component.numwords_write_b = dw,
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        altqpram_component.width_read_b = dw,
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        altqpram_component.widthad_read_b = aw,
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        altqpram_component.numwords_read_b = dw,
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        altqpram_component.indata_reg_a = "INCLOCK_A",
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        altqpram_component.wrcontrol_wraddress_reg_a = "INCLOCK_A",
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        altqpram_component.outdata_reg_a = "INCLOCK_A",
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        altqpram_component.indata_reg_b = "INCLOCK_B",
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        altqpram_component.wrcontrol_wraddress_reg_b = "INCLOCK_B",
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        altqpram_component.outdata_reg_b = "INCLOCK_B",
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        altqpram_component.indata_aclr_a = "INACLR_A",
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        altqpram_component.wraddress_aclr_a = "INACLR_A",
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        altqpram_component.wrcontrol_aclr_a = "INACLR_A",
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        altqpram_component.outdata_aclr_a = "INACLR_A",
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        altqpram_component.indata_aclr_b = "NONE",
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        altqpram_component.wraddress_aclr_b = "NONE",
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        altqpram_component.wrcontrol_aclr_b = "NONE",
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        altqpram_component.outdata_aclr_b = "INACLR_B",
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        altqpram_component.lpm_hint = "USE_ESB=ON";
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        //examplar attribute altqpram_component NOOPT TRUE
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323
`else
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//
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// Generic two-port synchronous RAM model
327
//
328
 
329
//
330
// Generic RAM's registers and wires
331
//
332
reg     [dw-1:0] mem [(1<<aw)-1:0];       // RAM content
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reg     [dw-1:0] do_reg_a;               // RAM data output register
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reg     [dw-1:0] do_reg_b;               // RAM data output register
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336
//
337
// Data output drivers
338
//
339
assign do_a = (oe_a) ? do_reg_a : {dw{1'b0}};
340
assign do_b = (oe_b) ? do_reg_b : {dw{1'b0}};
341
 
342
//
343
// RAM read and write
344
//
345
always @(posedge clk_a)
346
        if (ce_a && !we_a)
347
                do_reg_a <=  mem[addr_a];
348
 
349
always @(posedge clk_a)
350
        if (ce_a && we_a)
351
                mem[addr_a] <=  di_a;
352
 
353
//
354
// RAM read and write
355
//
356
always @(posedge clk_b)
357
        if (ce_b && !we_b)
358
                do_reg_b <=  mem[addr_b];
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always @(posedge clk_b)
360
        if (ce_b && we_b)
361
                mem[addr_b] <=  di_b;
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363
`endif  // !OR1200_ALTERA_LPM
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`endif  // !OR1200_XILINX_RAMB4_S16_S16
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`endif  // !OR1200_VIRAGE_STP
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`endif  // !OR1200_AVANT_ATP
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`endif  // !OR1200_ARTISAN_SDP
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endmodule

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