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[/] [claw/] [trunk/] [or1200_cpu/] [or1200_wb_biu.v] - Blame information for rev 4

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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  OR1200's WISHBONE BIU                                       ////
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////                                                              ////
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////  This file is part of the OpenRISC 1200 project              ////
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////  http://www.opencores.org/cores/or1k/                        ////
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////                                                              ////
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////  Description                                                 ////
9
////  Implements WISHBONE interface                               ////
10
////                                                              ////
11
////  To Do:                                                      ////
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////   - if biu_cyc/stb are deasserted and wb_ack_i is asserted   ////
13
////   and this happens even before aborted_r is asssrted,        ////
14
////   wb_ack_i will be delivered even though transfer is         ////
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////   internally considered already aborted. However most        ////
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////   wb_ack_i are externally registered and delayed. Normally   ////
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////   this shouldn't cause any problems.                         ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Damjan Lampret, lampret@opencores.org                 ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
48
//
49
// CVS Revision History
50
//
51
// $Log: not supported by cvs2svn $
52
// Revision 1.7  2004/04/05 08:29:57  lampret
53
// Merged branch_qmem into main tree.
54
//
55
// Revision 1.6.4.1  2003/07/08 15:36:37  lampret
56
// Added embedded memory QMEM.
57
//
58
// Revision 1.6  2003/04/07 20:57:46  lampret
59
// Fixed OR1200_CLKDIV_x_SUPPORTED defines. Fixed order of ifdefs.
60
//
61
// Revision 1.5  2002/12/08 08:57:56  lampret
62
// Added optional support for WB B3 specification (xwb_cti_o, xwb_bte_o). Made xwb_cab_o optional.
63
//
64
// Revision 1.4  2002/09/16 03:09:16  lampret
65
// Fixed a combinational loop.
66
//
67
// Revision 1.3  2002/08/12 05:31:37  lampret
68
// Added optional retry counter for wb_rty_i. Added graceful termination for aborted transfers.
69
//
70
// Revision 1.2  2002/07/14 22:17:17  lampret
71
// Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized.
72
//
73
// Revision 1.1  2002/01/03 08:16:15  lampret
74
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
75
//
76
// Revision 1.12  2001/11/22 13:42:51  lampret
77
// Added wb_cyc_o assignment after it was removed by accident.
78
//
79
// Revision 1.11  2001/11/20 21:28:10  lampret
80
// Added optional sampling of inputs.
81
//
82
// Revision 1.10  2001/11/18 11:32:00  lampret
83
// OR1200_REGISTERED_OUTPUTS can now be enabled.
84
//
85
// Revision 1.9  2001/10/21 17:57:16  lampret
86
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
87
//
88
// Revision 1.8  2001/10/14 13:12:10  lampret
89
// MP3 version.
90
//
91
// Revision 1.1.1.1  2001/10/06 10:18:35  igorm
92
// no message
93
//
94
// Revision 1.3  2001/08/09 13:39:33  lampret
95
// Major clean-up.
96
//
97
// Revision 1.2  2001/07/22 03:31:54  lampret
98
// Fixed RAM's oen bug. Cache bypass under development.
99
//
100
// Revision 1.1  2001/07/20 00:46:23  lampret
101
// Development version of RTL. Libraries are missing.
102
//
103
//
104
 
105
// synopsys translate_off
106
`include "timescale.v"
107
// synopsys translate_on
108
`include "or1200_defines.v"
109
 
110
module or1200_wb_biu(
111
        // RISC clock, reset and clock control
112
        clk, rst, clmode,
113
 
114
        // WISHBONE interface
115
        wb_clk_i, wb_rst_i, wb_ack_i, wb_err_i, wb_rty_i, wb_dat_i,
116
        wb_cyc_o, wb_adr_o, wb_stb_o, wb_we_o, wb_sel_o, wb_dat_o,
117
`ifdef OR1200_WB_CAB
118
        wb_cab_o,
119
`endif
120
`ifdef OR1200_WB_B3
121
        wb_cti_o, wb_bte_o,
122
`endif
123
 
124
        // Internal RISC bus
125
        biu_dat_i, biu_adr_i, biu_cyc_i, biu_stb_i, biu_we_i, biu_sel_i, biu_cab_i,
126
        biu_dat_o, biu_ack_o, biu_err_o
127
);
128
 
129
parameter dw = `OR1200_OPERAND_WIDTH;
130
parameter aw = `OR1200_OPERAND_WIDTH;
131
 
132
//
133
// RISC clock, reset and clock control
134
//
135
input                   clk;            // RISC clock
136
input                   rst;            // RISC reset
137
input   [1:0]            clmode;         // 00 WB=RISC, 01 WB=RISC/2, 10 N/A, 11 WB=RISC/4
138
 
139
//
140
// WISHBONE interface
141
//
142
input                   wb_clk_i;       // clock input
143
input                   wb_rst_i;       // reset input
144
input                   wb_ack_i;       // normal termination
145
input                   wb_err_i;       // termination w/ error
146
input                   wb_rty_i;       // termination w/ retry
147
input   [dw-1:0] wb_dat_i;       // input data bus
148
output                  wb_cyc_o;       // cycle valid output
149
output  [aw-1:0] wb_adr_o;       // address bus outputs
150
output                  wb_stb_o;       // strobe output
151
output                  wb_we_o;        // indicates write transfer
152
output  [3:0]            wb_sel_o;       // byte select outputs
153
output  [dw-1:0] wb_dat_o;       // output data bus
154
`ifdef OR1200_WB_CAB
155
output                  wb_cab_o;       // consecutive address burst
156
`endif
157
`ifdef OR1200_WB_B3
158
output  [2:0]            wb_cti_o;       // cycle type identifier
159
output  [1:0]            wb_bte_o;       // burst type extension
160
`endif
161
 
162
//
163
// Internal RISC interface
164
//
165
input   [dw-1:0] biu_dat_i;      // input data bus
166
input   [aw-1:0] biu_adr_i;      // address bus
167
input                   biu_cyc_i;      // WB cycle
168
input                   biu_stb_i;      // WB strobe
169
input                   biu_we_i;       // WB write enable
170
input                   biu_cab_i;      // CAB input
171
input   [3:0]            biu_sel_i;      // byte selects
172
output  [31:0]           biu_dat_o;      // output data bus
173
output                  biu_ack_o;      // ack output
174
output                  biu_err_o;      // err output
175
 
176
//
177
// Registers
178
//
179
reg     [1:0]            valid_div;      // Used for synchronization
180
`ifdef OR1200_REGISTERED_OUTPUTS
181
reg     [aw-1:0] wb_adr_o;       // address bus outputs
182
reg                     wb_cyc_o;       // cycle output
183
reg                     wb_stb_o;       // strobe output
184
reg                     wb_we_o;        // indicates write transfer
185
reg     [3:0]            wb_sel_o;       // byte select outputs
186
`ifdef OR1200_WB_CAB
187
reg                     wb_cab_o;       // CAB output
188
`endif
189
`ifdef OR1200_WB_B3
190
reg     [1:0]            burst_len;      // burst counter
191
reg     [2:0]            wb_cti_o;       // cycle type identifier
192
`endif
193
reg     [dw-1:0] wb_dat_o;       // output data bus
194
`endif
195
`ifdef OR1200_REGISTERED_INPUTS
196
reg                     long_ack_o;     // normal termination
197
reg                     long_err_o;     // error termination
198
reg     [dw-1:0] biu_dat_o;      // output data bus
199
`else
200
wire                    long_ack_o;     // normal termination
201
wire                    long_err_o;     // error termination
202
`endif
203
wire                    aborted;        // Graceful abort
204
reg                     aborted_r;      // Graceful abort
205
wire                    retry;          // Retry
206
`ifdef OR1200_WB_RETRY
207
reg     [`OR1200_WB_RETRY-1:0] retry_cntr;       // Retry counter
208
`endif
209
 
210
//
211
// WISHBONE I/F <-> Internal RISC I/F conversion
212
//
213
 
214
//
215
// Address bus
216
//
217
`ifdef OR1200_REGISTERED_OUTPUTS
218
always @(posedge wb_clk_i or posedge wb_rst_i)
219
        if (wb_rst_i)
220
                wb_adr_o <=  {aw{1'b0}};
221
        else if ((biu_cyc_i & biu_stb_i) & ~wb_ack_i & ~aborted & ~(wb_stb_o & ~wb_ack_i))
222
                wb_adr_o <=  biu_adr_i;
223
`else
224
assign wb_adr_o = biu_adr_i;
225
`endif
226
 
227
//
228
// Input data bus
229
//
230
`ifdef OR1200_REGISTERED_INPUTS
231
always @(posedge wb_clk_i or posedge wb_rst_i)
232
        if (wb_rst_i)
233
                biu_dat_o <=  32'h0000_0000;
234
        else if (wb_ack_i)
235
                biu_dat_o <=  wb_dat_i;
236
`else
237
assign biu_dat_o = wb_dat_i;
238
`endif
239
 
240
//
241
// Output data bus
242
//
243
`ifdef OR1200_REGISTERED_OUTPUTS
244
always @(posedge wb_clk_i or posedge wb_rst_i)
245
        if (wb_rst_i)
246
                wb_dat_o <=  {dw{1'b0}};
247
        else if ((biu_cyc_i & biu_stb_i) & ~wb_ack_i & ~aborted)
248
                wb_dat_o <=  biu_dat_i;
249
`else
250
assign wb_dat_o = biu_dat_i;
251
`endif
252
 
253
//
254
// Valid_div counts RISC clock cycles by modulo 4
255
// and is used to synchronize external WB i/f to
256
// RISC clock
257
//
258
always @(posedge clk or posedge rst)
259
        if (rst)
260
                valid_div <=  2'b0;
261
        else
262
                valid_div <=  valid_div + 1'd1;
263
 
264
//
265
// biu_ack_o is one RISC clock cycle long long_ack_o.
266
// long_ack_o is one, two or four RISC clock cycles long because
267
// WISHBONE can work at 1, 1/2 or 1/4 RISC clock.
268
//
269
assign biu_ack_o = long_ack_o
270
`ifdef OR1200_CLKDIV_2_SUPPORTED
271
                & (valid_div[0] | ~clmode[0])
272
`ifdef OR1200_CLKDIV_4_SUPPORTED
273
                & (valid_div[1] | ~clmode[1])
274
`endif
275
`endif
276
                ;
277
 
278
//
279
// Acknowledgment of the data to the RISC
280
//
281
// long_ack_o
282
//
283
`ifdef OR1200_REGISTERED_INPUTS
284
always @(posedge wb_clk_i or posedge wb_rst_i)
285
        if (wb_rst_i)
286
                long_ack_o <=  1'b0;
287
        else
288
                long_ack_o <=  wb_ack_i & ~aborted;
289
`else
290
assign long_ack_o = wb_ack_i & ~aborted_r;
291
`endif
292
 
293
//
294
// biu_err_o is one RISC clock cycle long long_err_o.
295
// long_err_o is one, two or four RISC clock cycles long because
296
// WISHBONE can work at 1, 1/2 or 1/4 RISC clock.
297
//
298
assign biu_err_o = long_err_o
299
`ifdef OR1200_CLKDIV_2_SUPPORTED
300
                & (valid_div[0] | ~clmode[0])
301
`ifdef OR1200_CLKDIV_4_SUPPORTED
302
                & (valid_div[1] | ~clmode[1])
303
`endif
304
`endif
305
                ;
306
 
307
//
308
// Error termination
309
//
310
// long_err_o
311
//
312
`ifdef OR1200_REGISTERED_INPUTS
313
always @(posedge wb_clk_i or posedge wb_rst_i)
314
        if (wb_rst_i)
315
                long_err_o <=  1'b0;
316
        else
317
                long_err_o <=  wb_err_i & ~aborted;
318
`else
319
assign long_err_o = wb_err_i & ~aborted_r;
320
`endif
321
 
322
//
323
// Retry counter
324
//
325
// Assert 'retry' when 'wb_rty_i' is sampled high and keep it high
326
// until retry counter doesn't expire
327
// 
328
`ifdef OR1200_WB_RETRY
329
assign retry = wb_rty_i | (|retry_cntr);
330
`else
331
assign retry = 1'b0;
332
`endif
333
`ifdef OR1200_WB_RETRY
334
always @(posedge wb_clk_i or posedge wb_rst_i)
335
        if (wb_rst_i)
336
                retry_cntr <=  1'b0;
337
        else if (wb_rty_i)
338
                retry_cntr <=  {`OR1200_WB_RETRY{1'b1}};
339
        else if (retry_cntr)
340
                retry_cntr <=  retry_cntr - 7'd1;
341
`endif
342
 
343
//
344
// Graceful completion of aborted transfers
345
//
346
// Assert 'aborted' when 1) current transfer is in progress (wb_stb_o; which
347
// we know is only asserted together with wb_cyc_o) 2) and in next WB clock cycle
348
// wb_stb_o would be deasserted (biu_cyc_i and biu_stb_i are low) 3) and
349
// there is no termination of current transfer in this WB clock cycle (wb_ack_i
350
// and wb_err_i are low).
351
// 'aborted_r' is registered 'aborted' and extended until this "aborted" transfer
352
// is properly terminated with wb_ack_i/wb_err_i.
353
// 
354
assign aborted = wb_stb_o & ~(biu_cyc_i & biu_stb_i) & ~(wb_ack_i | wb_err_i);
355
always @(posedge wb_clk_i or posedge wb_rst_i)
356
        if (wb_rst_i)
357
                aborted_r <=  1'b0;
358
        else if (wb_ack_i | wb_err_i)
359
                aborted_r <=  1'b0;
360
        else if (aborted)
361
                aborted_r <=  1'b1;
362
 
363
//
364
// WB cyc_o
365
//
366
// Either 1) normal transfer initiated by biu_cyc_i (and biu_cab_i if
367
// bursts are enabled) and possibly suspended by 'retry'
368
// or 2) extended "aborted" transfer
369
//
370
`ifdef OR1200_REGISTERED_OUTPUTS
371
always @(posedge wb_clk_i or posedge wb_rst_i)
372
        if (wb_rst_i)
373
                wb_cyc_o <=  1'b0;
374
        else
375
`ifdef OR1200_NO_BURSTS
376
                wb_cyc_o <=  biu_cyc_i & ~wb_ack_i & ~retry | aborted & ~wb_ack_i;
377
`else
378
                wb_cyc_o <=  biu_cyc_i & ~wb_ack_i & ~retry | biu_cab_i | aborted & ~wb_ack_i;
379
`endif
380
`else
381
`ifdef OR1200_NO_BURSTS
382
assign wb_cyc_o = biu_cyc_i & ~retry;
383
`else
384
assign wb_cyc_o = biu_cyc_i | biu_cab_i & ~retry;
385
`endif
386
`endif
387
 
388
//
389
// WB stb_o
390
//
391
`ifdef OR1200_REGISTERED_OUTPUTS
392
always @(posedge wb_clk_i or posedge wb_rst_i)
393
        if (wb_rst_i)
394
                wb_stb_o <=  1'b0;
395
        else
396
                wb_stb_o <=  (biu_cyc_i & biu_stb_i) & ~wb_ack_i & ~retry | aborted & ~wb_ack_i;
397
`else
398
assign wb_stb_o = biu_cyc_i & biu_stb_i;
399
`endif
400
 
401
//
402
// WB we_o
403
//
404
`ifdef OR1200_REGISTERED_OUTPUTS
405
always @(posedge wb_clk_i or posedge wb_rst_i)
406
        if (wb_rst_i)
407
                wb_we_o <=  1'b0;
408
        else
409
                wb_we_o <=  biu_cyc_i & biu_stb_i & biu_we_i | aborted & wb_we_o;
410
`else
411
assign wb_we_o = biu_cyc_i & biu_stb_i & biu_we_i;
412
`endif
413
 
414
//
415
// WB sel_o
416
//
417
`ifdef OR1200_REGISTERED_OUTPUTS
418
always @(posedge wb_clk_i or posedge wb_rst_i)
419
        if (wb_rst_i)
420
                wb_sel_o <=  4'b0000;
421
        else
422
                wb_sel_o <=  biu_sel_i;
423
`else
424
assign wb_sel_o = biu_sel_i;
425
`endif
426
 
427
`ifdef OR1200_WB_CAB
428
//
429
// WB cab_o
430
//
431
`ifdef OR1200_REGISTERED_OUTPUTS
432
always @(posedge wb_clk_i or posedge wb_rst_i)
433
        if (wb_rst_i)
434
                wb_cab_o <=  1'b0;
435
        else
436
                wb_cab_o <=  biu_cab_i;
437
`else
438
assign wb_cab_o = biu_cab_i;
439
`endif
440
`endif
441
 
442
`ifdef OR1200_WB_B3
443
//
444
// Count burst beats
445
//
446
always @(posedge wb_clk_i or posedge wb_rst_i)
447
        if (wb_rst_i)
448
                burst_len <=  2'b00;
449
        else if (biu_cab_i && burst_len && wb_ack_i)
450
                burst_len <=  burst_len - 1'b1;
451
        else if (~biu_cab_i)
452
                burst_len <=  2'b11;
453
 
454
//
455
// WB cti_o
456
//
457
`ifdef OR1200_REGISTERED_OUTPUTS
458
always @(posedge wb_clk_i or posedge wb_rst_i)
459
        if (wb_rst_i)
460
                wb_cti_o <=  3'b000;    // classic cycle
461
`ifdef OR1200_NO_BURSTS
462
        else
463
                wb_cti_o <=  3'b111;    // end-of-burst
464
`else
465
        else if (biu_cab_i && burst_len[1])
466
                wb_cti_o <=  3'b010;    // incrementing burst cycle
467
        else if (biu_cab_i && wb_ack_i)
468
                wb_cti_o <=  3'b111;    // end-of-burst
469
`endif  // OR1200_NO_BURSTS
470
`else
471
Unsupported !!!;
472
`endif
473
 
474
//
475
// WB bte_o
476
//
477
assign wb_bte_o = 2'b01;        // 4-beat wrap burst
478
 
479
`endif  // OR1200_WB_B3
480
 
481
endmodule

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