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[/] [claw/] [trunk/] [or1200_cpu/] [or1200_wbmux.v] - Blame information for rev 4

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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  OR1200's Write-back Mux                                     ////
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////                                                              ////
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////  This file is part of the OpenRISC 1200 project              ////
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////  http://www.opencores.org/cores/or1k/                        ////
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////                                                              ////
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////  Description                                                 ////
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////  CPU's write-back stage of the pipeline                      ////
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////                                                              ////
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////  To Do:                                                      ////
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////   - make it smaller and faster                               ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Damjan Lampret, lampret@opencores.org                 ////
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////  Modified by:                                                ////
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////      - Balaji V. Iyer, bviyer@ncsu.edu                       ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
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// Revision 1.2  2002/03/29 15:16:56  lampret
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// Some of the warnings fixed.
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//
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// Revision 1.1  2002/01/03 08:16:15  lampret
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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//
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// Revision 1.8  2001/10/21 17:57:16  lampret
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// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
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//
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// Revision 1.7  2001/10/14 13:12:10  lampret
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// MP3 version.
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//
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// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
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// no message
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//
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// Revision 1.2  2001/08/09 13:39:33  lampret
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// Major clean-up.
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//
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// Revision 1.1  2001/07/20 00:46:23  lampret
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// Development version of RTL. Libraries are missing.
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//
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//
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// synopsys translate_off
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`include "timescale.v"
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// synopsys translate_on
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`include "or1200_defines.v"
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module or1200_wbmux(
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        // Clock and reset
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        clk, rst,
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        // Internal i/f
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        wb_freeze, rfwb_op,rfwb_op2,
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        muxin_a, muxin_b, muxin_c, muxin_d,
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        muxin_a2, muxin_b2, muxin_c2, muxin_d2,
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        muxout, muxreg, muxreg_valid,
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        muxout2, muxreg2, muxreg2_valid,
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        thread_in, thread_out
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);
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parameter width = 32; //`OR1200_OPERAND_WIDTH;
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//
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// I/O
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//
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//
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// Clock and reset
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//
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input                           clk;
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input                           rst;
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//
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// Internal i/f
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//
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input                           wb_freeze;
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input   [`OR1200_RFWBOP_WIDTH-1:0]       rfwb_op;
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input   [`OR1200_RFWBOP_WIDTH-1:0]       rfwb_op2;
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input   [width-1:0]              muxin_a;
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input   [width-1:0]              muxin_b;
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input   [width-1:0]              muxin_c;
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input   [width-1:0]              muxin_d;
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input   [width-1:0]              muxin_a2;
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input   [width-1:0]              muxin_b2;
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input   [width-1:0]              muxin_c2;
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input   [width-1:0]              muxin_d2;
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output  [width-1:0]              muxout;
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output  [width-1:0]              muxout2;
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output  [width-1:0]              muxreg;
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output  [width-1:0]              muxreg2;
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output                          muxreg_valid;
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output                          muxreg2_valid;
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input [2:0]      thread_in;
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output[2:0]      thread_out;
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reg[2:0] thread_out;
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//
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// Internal wires and regs
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//
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reg     [width-1:0]              muxout;
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reg     [width-1:0]              muxreg;
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reg                             muxreg_valid;
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reg     [width-1:0]              muxout2;
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reg     [width-1:0]              muxreg2;
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reg                             muxreg2_valid;
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//
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// Registered output from the write-back multiplexer
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//
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always @(posedge clk or posedge rst) begin
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        if (rst) begin
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                muxreg <=  32'd0;
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                muxreg2 <=  32'd0;              // bviyer
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                muxreg_valid <=  1'b0;
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                muxreg2_valid <=  1'b0; // bviyer
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                thread_out <= 3'b0;
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        end
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        else if (!wb_freeze) begin
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                muxreg <=  muxout;
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                muxreg2 <=  muxout2;            // bviyer
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                muxreg_valid <=  rfwb_op[0];
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                muxreg2_valid <=  rfwb_op2[0]; // bviyer
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                thread_out <= thread_in;
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        end
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end
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//
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// Write-back multiplexer
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//
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always @(muxin_a or muxin_b or muxin_c or muxin_d or rfwb_op) begin
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`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
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        case(rfwb_op[`OR1200_RFWBOP_WIDTH-1:1]) // synopsys parallel_case infer_mux
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`else
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        case(rfwb_op[`OR1200_RFWBOP_WIDTH-1:1]) // synopsys parallel_case
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`endif
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                2'b00: muxout = muxin_a;
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                2'b01: begin
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                        muxout = muxin_b;
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`ifdef OR1200_VERBOSE
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// synopsys translate_off
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                        $display("  WBMUX: muxin_b %h", muxin_b);
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// synopsys translate_on
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`endif
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                end
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                2'b10: begin
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                        muxout = muxin_c;
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`ifdef OR1200_VERBOSE
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// synopsys translate_off
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                        $display("  WBMUX: muxin_c %h", muxin_c);
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// synopsys translate_on
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`endif
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                end
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                2'b11: begin
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                        muxout = muxin_d + 4'h8;
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`ifdef OR1200_VERBOSE
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// synopsys translate_off
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                        $display("  WBMUX: muxin_d %h", muxin_d + 4'h8);
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// synopsys translate_on
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`endif
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                end
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        endcase
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end
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//
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// Write-back multiplexer
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//
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// bviyer: added the 2-way capability
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always @(muxin_a2 or muxin_b2 or muxin_c2 or muxin_d2 or rfwb_op2) begin
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`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
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        case(rfwb_op2[`OR1200_RFWBOP_WIDTH-1:1]) // synopsys parallel_case infer_mux
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`else
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        case(rfwb_op2[`OR1200_RFWBOP_WIDTH-1:1]) // synopsys parallel_case
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`endif
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                2'b00: muxout2 = muxin_a2;
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                2'b01: begin
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                        muxout2 = muxin_b2;
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`ifdef OR1200_VERBOSE
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// synopsys translate_off
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        $display("  WBMUX: muxin_b %h", muxin_b2);
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// synopsys translate_on
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`endif
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                end
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                2'b10: begin
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                        muxout2 = muxin_c2;
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`ifdef OR1200_VERBOSE
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// synopsys translate_off
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        $display("  WBMUX: muxin_c %h", muxin_c2);
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// synopsys translate_on
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`endif
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                end
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                2'b11: begin
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                        muxout2 = muxin_d2 + 4'h8;
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`ifdef OR1200_VERBOSE
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// synopsys translate_off
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        $display("  WBMUX: muxin_d %h", muxin_d2 + 4'h8);
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// synopsys translate_on
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`endif
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                end
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        endcase
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end
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// assign thread_out = thread_in;
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endmodule

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