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[/] [claw/] [trunk/] [or1200_cpu/] [tb_or1200_cpu.v] - Blame information for rev 4

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`include "timescale.v"
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`include "or1200_defines.v"
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module tb_or1200_cpu();
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parameter dw=32;
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parameter aw=5;
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reg                           clk;
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reg                           rst;
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wire                          ic_en;
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wire  [31:0]                  icpu_adr_o;
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wire                          icpu_cycstb_o;
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wire  [3:0]                   icpu_sel_o;
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wire  [3:0]                   icpu_tag_o;
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reg   [63:0]                  icpu_dat_i;
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reg                           icpu_ack_i;
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reg                           icpu_rty_i;
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reg                           icpu_err_i;
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reg   [31:0]                  icpu_adr_i;
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wire                          immu_en;
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wire  [31:0]                  ex_insn;
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wire  [31:0]                  ex_insn2;
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wire                          ex_freeze;
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wire  [31:0]                  id_pc;
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wire  [`OR1200_BRANCHOP_WIDTH-1:0]    branch_op;
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reg                           du_stall;
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reg   [dw-1:0]                du_addr;
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reg   [dw-1:0]                du_dat_du;
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reg                           du_read;
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reg                           du_write;
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reg   [`OR1200_DU_DSR_WIDTH-1:0]      du_dsr;
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reg                           du_hwbkpt;
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wire  [12:0]                  du_except;
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wire  [dw-1:0]                du_dat_cpu;
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wire  [dw-1:0]                rf_dataw;
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reg [3:0]                      icpu_tag_i;
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wire  [31:0]                  dcpu_adr_o;
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wire                          dcpu_cycstb_o;
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wire                          dcpu_we_o;
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wire  [3:0]                   dcpu_sel_o;
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wire  [3:0]                   dcpu_tag_o;
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wire  [31:0]                  dcpu_dat_o;
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wire  [31:0]                  dcpu_adr_o2;
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wire                          dcpu_cycstb_o2;
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wire                          dcpu_we_o2;
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wire  [3:0]                   dcpu_sel_o2;
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wire  [3:0]                   dcpu_tag_o2;
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wire  [31:0]                  dcpu_dat_o2;
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reg   [31:0]                  dcpu_dat_i;
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reg                           dcpu_ack_i;
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reg                           dcpu_rty_i;
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reg                           dcpu_err_i;
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reg   [3:0]                   dcpu_tag_i;
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wire                          dc_en;
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wire                          dmmu_en;
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wire                          supv;
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reg   [dw-1:0]                spr_dat_pic;
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reg   [dw-1:0]                spr_dat_tt;
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reg   [dw-1:0]                spr_dat_pm;
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reg   [dw-1:0]                spr_dat_dmmu;
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reg   [dw-1:0]                spr_dat_immu;
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reg   [dw-1:0]                spr_dat_du;
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wire  [dw-1:0]                spr_addr;
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wire  [dw-1:0]                spr_addr2;
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wire  [dw-1:0]                spr_dat_cpu;
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wire  [dw-1:0]                spr_dat_npc;
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reg                           sig_int;
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reg                           sig_tick;
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wire [31:0]                      spr_cs;
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wire [31:0]                      spr_cs2;
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or1200_cpu or1200_cpu(
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        // Clk & Rst
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        clk, rst,
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        // Insn interface
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        ic_en,
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        icpu_adr_o, icpu_cycstb_o, icpu_sel_o, icpu_tag_o,
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        icpu_dat_i, icpu_ack_i, icpu_rty_i, icpu_err_i, icpu_adr_i, icpu_tag_i,
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        immu_en,
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        // Debug unit
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        ex_insn, ex_freeze, id_pc, branch_op,
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        ex_insn2,               // bviyer
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        spr_dat_npc, rf_dataw,
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        du_stall, du_addr, du_dat_du, du_read, du_write, du_dsr, du_hwbkpt,
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        du_except, du_dat_cpu,
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        // Data interface
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        dc_en,
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        dcpu_adr_o,dcpu_cycstb_o, dcpu_we_o, dcpu_sel_o, dcpu_tag_o, dcpu_dat_o,
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        dcpu_adr_o2,dcpu_cycstb_o2, dcpu_we_o2,
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        dcpu_sel_o2, dcpu_tag_o2, dcpu_dat_o2,
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        dcpu_dat_i, dcpu_ack_i, dcpu_rty_i, dcpu_err_i, dcpu_tag_i,
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        // dcpu_dat_i2,dcpu_ack_i2,dcpu_rty_i2,dcpu_err_i2,dcpu_tag_i2,
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        dmmu_en,
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        // Interrupt & tick exceptions
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        sig_int, sig_tick,
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        // SPR interface
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        supv, spr_addr, spr_addr2, spr_dat_cpu, spr_dat_pic, spr_dat_tt,
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        spr_dat_pm,
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        spr_dat_dmmu, spr_dat_immu, spr_dat_du, spr_cs, spr_cs2, spr_we
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);
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initial begin
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  #0     rst=0;
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        clk=0;
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  #5    rst=1;
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  #5    rst=0;
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  #10   rst=0;
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        du_stall=0;
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        icpu_rty_i=0;
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        icpu_adr_i=32'b0;
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        icpu_dat_i=64'h1500000015000000;
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        icpu_ack_i=1'b0;
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        icpu_err_i=0;
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        // icpu_tag_i=4'b0; // `OR1200_ITAG_PE;
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        dcpu_ack_i=1'b1;
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        dcpu_err_i=1;
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        dcpu_tag_i=4'b0;
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        dcpu_dat_i=32'hABCDEF12;
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end
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always #5 clk = ~clk;
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endmodule

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