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[/] [claw/] [trunk/] [or1200_cpu/] [tb_or1200_ic_ram.v] - Blame information for rev 4

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1 2 conte
`include "timescale.v"
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`include "or1200_defines.v"
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////////////////////////////////////////////////////////////
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//
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// Author: Balaji V. Iyer, bviyer@ncsu.edu
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// $Id: tb_or1200_ic_ram.v,v 1.1.1.1 2004-09-02 21:36:52 conte Exp $
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// $Log: not supported by cvs2svn $
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// $Revision: 1.1.1.1 $
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////////////////////////////////////////////////////////////
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module tb_or1200_ic_ram();
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parameter dw = `OR1200_OPERAND_WIDTH;   // value is 32
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parameter aw = `OR1200_ICINDX;          // value is 11
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wire[63:0] dataout;
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reg clk,rst;
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reg [aw-1:0] addr;
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reg [3:0] we;
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reg [63:0] datain;
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reg en;
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initial begin
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//  #100 $finish;
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end
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initial begin
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  #0     rst = 1;
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        we = 0;
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        en = 0;
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        clk= 0;
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        addr =11'b0;
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  #20   rst = 0;
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        en = 1;
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        addr= 11'b0;
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  #10   addr= 11'd2;
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  #10   addr= 11'd4;
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  #10   addr= 11'd6;
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end
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always #5 clk = ~clk;
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or1200_ic_ram or1200_ic_ram(.clk(clk), .rst(rst), .dataout(dataout),
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  .addr(addr), .en(en), .we(we), .datain(datain));
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endmodule

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