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[/] [claw/] [trunk/] [or1200_cpu/] [tb_or1200_ic_top.v] - Blame information for rev 4

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`define "timescale.v"
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`define "or1200_defines.v"
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module tb_or1200_ic_top();
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reg                           clk;
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reg                           rst;
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wire  [dw-1:0]                icbiu_dat_o;
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wire  [31:0]                  icbiu_adr_o;
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wire                          icbiu_cyc_o;
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wire                          icbiu_stb_o;
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wire                          icbiu_we_o;
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wire  [3:0]                   icbiu_sel_o;
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wire                          icbiu_cab_o;
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reg   [dw-1:0]                icbiu_dat_i;
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reg                           icbiu_ack_i;
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reg                           icbiu_err_i;
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reg                           ic_en;
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reg   [31:0]                  icqmem_adr_i;
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reg                           icqmem_cycstb_i;
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reg                           icqmem_ci_i;
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reg   [3:0]                   icqmem_sel_i;
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reg   [3:0]                   icqmem_tag_i;
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wire  [dw-1:0]                icqmem_dat_o;
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wire                          icqmem_ack_o;
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wire                          icqmem_rty_o;
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wire                          icqmem_err_o;
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wire  [3:0]                   icqmem_tag_o;
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`ifdef OR1200_BIST
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reg mbist_si_i;
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reg [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
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wire mbist_so_o;
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`endif
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reg                           spr_cs;
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reg                           spr_write;
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reg   [31:0]                  spr_dat_i;
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initial begin
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#0       rst=0;
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        clk=0;
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#5      rst=1;
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#10     rst=0;
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        ic_en=1'b1;
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