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[/] [claw/] [trunk/] [or1200_cpu/] [tb_or1200_operandmuxes.v] - Blame information for rev 4

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1 2 conte
`include "timescale.v"
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`include "or1200_defines.v"
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////////////////////////////////////////////////////////////////////
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//// Author: Balaji V. Iyer, bviyer@ncsu.edu                    ////
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////////////////////////////////////////////////////////////////////
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module tb_or1200_operandmuxes();
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reg clk;
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reg rst;
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reg id_freeze;
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reg ex_freeze;
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reg[31:0] rf_dataa;
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reg[31:0] rf_datab;
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reg[31:0] rf_dataa2;
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reg[31:0] rf_datab2;
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reg[31:0] ex_forw;
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reg[31:0] wb_forw;
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reg[31:0] ex_forw2;
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reg[31:0] wb_forw2;
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reg[31:0] simm;
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reg[31:0] simm2;
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reg[`OR1200_SEL_WIDTH-1:0] sel_a;
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reg[`OR1200_SEL_WIDTH-1:0] sel_b;
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reg[`OR1200_SEL_WIDTH-1:0] sel_a2;
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reg[`OR1200_SEL_WIDTH-1:0] sel_b2;
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wire [31:0] operand_a;
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wire [31:0] operand_b;
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wire [31:0] operand_a2;
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wire [31:0] operand_b2;
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wire [31:0] muxed_b;
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wire [31:0] muxed_b2;
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or1200_operandmuxes or1200_operandmuxes(.clk(clk), .rst(rst),
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         .id_freeze(id_freeze), .ex_freeze(ex_freeze), .rf_dataa(rf_dataa),
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        .rf_datab(rf_datab), .rf_dataa2(rf_dataa2), .rf_datab2(rf_datab2),
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        .ex_forw(ex_forw), .wb_forw(wb_forw), .ex_forw2(ex_forw2),
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        .wb_forw2(wb_forw2), .simm(simm), .simm2(simm2), .sel_a(sel_a),
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        .sel_b(sel_b), .sel_a2(sel_a2), .sel_b2(sel_b2), .operand_a(operand_a),
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        .operand_b(operand_b), .operand_a2(operand_a2),.operand_b2(operand_b2),
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        .muxed_b(muxed_b),.muxed_b2(muxed_b2));
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initial begin
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#0       rst=0;
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        clk=0;
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#10     rst=1;
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#10     rst=0;
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        ex_freeze=0;
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        id_freeze=0;
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        ex_forw=32'h12345678;
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        wb_forw=32'h90ABCDEF;
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        ex_forw2=32'h23456781;
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        wb_forw2=32'h0ABCDEF9;
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        rf_dataa = 32'hBA1A7EEE;        // yeye this almost spells my name
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        rf_datab= 32'hEEE7A1AB;
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        rf_dataa2= 32'h1A7EEEBA;
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        rf_datab2= 32'hE7A1ABEE;
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        sel_a=`OR1200_SEL_EX_FORW;
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        sel_a2=32'b0;
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        sel_b=`OR1200_SEL_WB_FORW;
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        sel_b2=32'b0;
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#10     rst=0;
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        ex_freeze=0;
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        id_freeze=0;
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        rf_dataa= 32'hBA1A7EEE;         // yeye this almost spells my name
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        rf_datab= 32'hEEE7A1AB;
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        rf_dataa2= 32'h1A7EEEBA;
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        rf_datab2= 32'hE7A1ABEE;
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        ex_forw=32'h12345678;
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        wb_forw=32'h90ABCDEF;
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        ex_forw2=32'h23456781;
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        wb_forw2=32'h0ABCDEF9;
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        sel_a2=`OR1200_SEL_EX_FORW;
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        sel_a=32'b0;
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        sel_b2=`OR1200_SEL_WB_FORW;
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        sel_b=32'b0;
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end
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always #5 clk = ~clk;
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endmodule

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