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[/] [claw/] [trunk/] [or1200_cpu/] [tb_or1200_rf.v] - Blame information for rev 4

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////////////////////////////////////////////////////////////////////
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////  Author:                                                   ////
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////     - Balaji V. Iyer, bviyer@ncsu.edu                      ////
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////////////////////////////////////////////////////////////////////
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`include "timescale.v"
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`include "or1200_defines.v"
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module tb_or1200_rf();
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parameter aw = 5;  //`OR1200_REGFILE_ADDR_WIDTH;
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parameter dw = 32;// `OR1200_OPERAND_WIDTH;
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reg clk;
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reg rst;
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reg supv;
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reg wb_freeze;
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reg [aw-1:0] addrw;
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reg [dw-1:0] dataw;
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reg we;
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reg we2;
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reg flushpipe;
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reg [aw-1:0] addrw2;
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reg [dw-1:0] dataw2;
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reg id_freeze;
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reg [aw-1:0] addra;
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reg [aw-1:0] addrb;
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wire [dw-1:0] dataa;
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wire [dw-1:0] datab;
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reg rda;
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reg rdb;
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reg [aw-1:0] addra2;
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reg [aw-1:0] addrb2;
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wire [dw-1:0] dataa2;
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wire [dw-1:0] datab2;
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reg rda2;
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reg rdb2;
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reg spr_cs;
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reg spr_write;
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reg [31:0] spr_addr;
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reg [31:0] spr_dat_i;
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wire [31:0] spr_dat_o;
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or1200_rf or1200_rf(.clk(clk), .rst(rst), .supv(supv), .wb_freeze(wb_freeze),
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  .addrw(addrw), .dataw(dataw), .addrw2(addrw2), .dataw2(dataw2), .we(we),
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  .we2(we2), .flushpipe (flushpipe), .id_freeze(id_freeze), .addra(addra),
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  .addrb(addrb), .dataa(dataa), .datab(datab), .rda(rda), .rdb(rdb),
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  .addra2(addra2), .addrb2(addrb2), .dataa2(dataa2),
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  .datab2(datab2), .rda2(rda2), .rdb2(rdb2), .spr_cs(spr_cs),
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  .spr_write(spr_write), .spr_addr(spr_addr), .spr_dat_i(spr_dat_i),
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  .spr_dat_o(spr_dat_o));
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initial begin
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  #0     clk=0;
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        rst=0;
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  #10   rst=1;
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  #10   rst=0;
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        wb_freeze=0;
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        flushpipe=0;
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        spr_cs=0;
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        spr_addr=32'b0;
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        spr_write=0;
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        addrw =5'd1;
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        addrw2=5'd2;
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        we=1;
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        we2=1;
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        rda=0;
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        rda2=0;
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        supv=1;
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        dataw =32'h12345678;
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        dataw2 =32'h90ABCDEF;
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  #10   id_freeze=0;
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  #20   spr_write=0;
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        id_freeze=0;
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        we=0;
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        we2=0;
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        rda=1;
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        rda2=1;
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        addra=5'd1;
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        addra2=5'd2;
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  #20   rst=0;
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        wb_freeze=0;
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        flushpipe=0;
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        spr_cs=0;
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        spr_addr[10:5]=6'b0;
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        spr_write=0;
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        addrw =5'd13;
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        addrw2=5'd14;
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        rda=0;
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        rda2=0;
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        we=1;
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        we2=1;
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        supv=1;
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        dataw =32'h23456789;
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        dataw2 =32'h0ABCDEF1;
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  #20   spr_write=0;
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        id_freeze=0;
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        we=0;
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        we2=0;
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        rdb=1;
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        rdb2=1;
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        addrb=5'd13;
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        addrb2=5'd14;
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end
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always #5 clk = ~clk;
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endmodule

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