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[/] [claw/] [trunk/] [or1200_cpu/] [view_command.log] - Blame information for rev 4

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                        Design Analyzer (TM)
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                      Behavioral Compiler (TM)
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                        DC Professional (TM)
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                           DC Expert (TM)
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                            DC Ultra (TM)
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                         VHDL Compiler (TM)
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                          HDL Compiler (TM)
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                        Library Compiler (TM)
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                         Power Compiler (TM)
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                          DFT Compiler (TM)
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                            BSD Compiler
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                      DesignWare Developer (TM)
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                          DesignPower (TM)
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            Version 2001.08 for sparcOS5 -- Aug 08, 2001
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              Copyright (c) 1988-2001 by Synopsys, Inc.
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                         ALL RIGHTS RESERVED
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design_analyzer> include or1200_cpu.sc > output.dat
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design_analyzer> create_schematic -size infinite    -gen_database
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Loading db file '/afs/eos.ncsu.edu/dist/cad446/local/TSMC025_deep/generic.sdb'
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Loading db file '/afs/eos.ncsu.edu/dist/cad446/local/TSMC025_deep/ncsulib25_symbols.sdb'
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Loading db file '/afs/eos.ncsu.edu/dist/cad446/local/TSMC025_deep/basic.sdb'
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Loading db file '/afs/bp.ncsu.edu/dist/synopsys200108/libraries/syn/1_25.font'
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design_analyzer>
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Thank you...

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