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[/] [claw/] [trunk/] [or1200_cpu/] [work/] [or1200_spram_64x24/] [_primary.vhd] - Blame information for rev 2

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Line No. Rev Author Line
1 2 conte
library verilog;
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use verilog.vl_types.all;
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entity or1200_spram_64x24 is
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    generic(
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        aw              : integer := 6;
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        dw              : integer := 24
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    );
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    port(
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        clk             : in     vl_logic;
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        rst             : in     vl_logic;
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        ce              : in     vl_logic;
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        we              : in     vl_logic;
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        oe              : in     vl_logic;
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        addr            : in     vl_logic_vector;
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        di              : in     vl_logic_vector;
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        do              : out    vl_logic_vector
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    );
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end or1200_spram_64x24;

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