| 1 |
11 |
N.Boukadid |
#
|
| 2 |
|
|
# File import script for the Wupper-Interlaken core hdl project
|
| 3 |
|
|
#
|
| 4 |
|
|
#
|
| 5 |
|
|
|
| 6 |
|
|
#Script Configuration for vc709
|
| 7 |
|
|
|
| 8 |
|
|
set proj_name core1990_interlaken
|
| 9 |
|
|
# Set the supportfiles directory path
|
| 10 |
|
|
set scriptdir [pwd]
|
| 11 |
|
|
set proj_dir $scriptdir/../
|
| 12 |
|
|
|
| 13 |
|
|
#Close currently open project and create a new one. (OVERWRITES PROJECT!!)
|
| 14 |
|
|
close_project -quiet
|
| 15 |
|
|
|
| 16 |
|
|
create_project -force -part xc7vx690tffg1761-2 $proj_name $proj_dir/projects/$proj_name
|
| 17 |
|
|
|
| 18 |
|
|
|
| 19 |
|
|
set_property target_language VHDL [current_project]
|
| 20 |
|
|
set_property default_lib work [current_project]
|
| 21 |
|
|
|
| 22 |
|
|
# ----------------------------------------------------------
|
| 23 |
|
|
# example application
|
| 24 |
|
|
# ----------------------------------------------------------
|
| 25 |
|
|
|
| 26 |
|
|
read_vhdl -library work $proj_dir/sources/interlaken_wrapper_vc709.vhd
|
| 27 |
|
|
read_vhdl -library work $proj_dir/sources/interlaken_pkg.vhd
|
| 28 |
|
|
|
| 29 |
|
|
close [ open $proj_dir/constraints/probes.xdc w ]
|
| 30 |
|
|
read_xdc -verbose $proj_dir/constraints/probes.xdc
|
| 31 |
|
|
set_property target_constrs_file $proj_dir/constraints/probes.xdc [current_fileset -constrset]
|
| 32 |
|
|
set_property STEPS.ROUTE_DESIGN.ARGS.DIRECTIVE MoreGlobalIterations [get_runs impl_1]
|
| 33 |
|
|
|
| 34 |
|
|
|
| 35 |
|
|
# ----------------------------------------------------------
|
| 36 |
|
|
# Core1990Interlaken top file
|
| 37 |
|
|
# ----------------------------------------------------------
|
| 38 |
|
|
read_vhdl -library work $proj_dir/sources/interlaken/interlaken_interface_vc709.vhd
|
| 39 |
|
|
|
| 40 |
|
|
add_files -fileset sim_1 -norecurse $proj_dir/simulation/interlaken_interface_tb.vhd
|
| 41 |
|
|
|
| 42 |
|
|
# ----------------------------------------------------------
|
| 43 |
|
|
# Interlaken CRC
|
| 44 |
|
|
# ----------------------------------------------------------
|
| 45 |
|
|
read_vhdl -library work $proj_dir/sources/interlaken/crc/crc-24.vhd
|
| 46 |
|
|
read_vhdl -library work $proj_dir/sources/interlaken/crc/crc-32.vhd
|
| 47 |
|
|
|
| 48 |
|
|
# ----------------------------------------------------------
|
| 49 |
|
|
# Interlaken Transmitter
|
| 50 |
|
|
# ----------------------------------------------------------
|
| 51 |
|
|
|
| 52 |
|
|
# BLOCK_SYNC_SM Module
|
| 53 |
|
|
# Generated by Xilinx 7 Series FPGAs Transceivers Wizard
|
| 54 |
|
|
read_vhdl -library work $proj_dir/sources/interlaken/transceiver/transceiver_10g_64b67b_block_sync_sm.vhd
|
| 55 |
|
|
#
|
| 56 |
|
|
|
| 57 |
|
|
read_vhdl -library work $proj_dir/sources/interlaken/transmitter/framing_burst.vhd
|
| 58 |
|
|
read_vhdl -library work $proj_dir/sources/interlaken/transmitter/framing_meta.vhd
|
| 59 |
|
|
read_vhdl -library work $proj_dir/sources/interlaken/transmitter/scrambler.vhd
|
| 60 |
|
|
read_vhdl -library work $proj_dir/sources/interlaken/transmitter/encoder.vhd
|
| 61 |
|
|
read_vhdl -library work $proj_dir/sources/interlaken/transmitter/interlaken_transmitter.vhd
|
| 62 |
|
|
|
| 63 |
|
|
# ----------------------------------------------------------
|
| 64 |
|
|
# Interlaken Receiver
|
| 65 |
|
|
# ----------------------------------------------------------
|
| 66 |
|
|
|
| 67 |
|
|
read_vhdl -library work $proj_dir/sources/interlaken/receiver/deframing_burst.vhd
|
| 68 |
|
|
read_vhdl -library work $proj_dir/sources/interlaken/receiver/deframing_meta.vhd
|
| 69 |
|
|
read_vhdl -library work $proj_dir/sources/interlaken/receiver/descrambler.vhd
|
| 70 |
|
|
read_vhdl -library work $proj_dir/sources/interlaken/receiver/decoder.vhd
|
| 71 |
|
|
read_vhdl -library work $proj_dir/sources/interlaken/receiver/interlaken_receiver.vhd
|
| 72 |
|
|
|
| 73 |
|
|
# ----------------------------------------------------------
|
| 74 |
|
|
# Interlaken Tests
|
| 75 |
|
|
# ----------------------------------------------------------
|
| 76 |
|
|
read_vhdl -library work $proj_dir/sources/interlaken/test/data_generator.vhd
|
| 77 |
|
|
read_vhdl -library work $proj_dir/sources/interlaken/test/pipeline.vhd
|
| 78 |
|
|
|
| 79 |
|
|
# ----------------------------------------------------------
|
| 80 |
|
|
# IP cores (Interlaken)
|
| 81 |
|
|
# ----------------------------------------------------------
|
| 82 |
|
|
|
| 83 |
|
|
import_ip $proj_dir/sources/ip_cores/vc709/clk_40MHz.xci
|
| 84 |
|
|
import_ip $proj_dir/sources/ip_cores/vc709/Transceiver_10g_64b67b.xci
|
| 85 |
|
|
import_ip $proj_dir/sources/ip_cores/vc709/RX_FIFO.xci
|
| 86 |
|
|
import_ip $proj_dir/sources/ip_cores/vc709/TX_FIFO.xci
|
| 87 |
|
|
|
| 88 |
|
|
import_ip $proj_dir/sources/ip_cores/vc709/ila_data.xci
|
| 89 |
|
|
import_ip $proj_dir/sources/ip_cores/vc709/vio_0.xci
|
| 90 |
|
|
|
| 91 |
|
|
# Generate all the output products
|
| 92 |
|
|
generate_target all [get_files *clk_40MHz.xci]
|
| 93 |
|
|
# Create a DCP for the IP
|
| 94 |
|
|
synth_ip [get_files *clk_40MHz.xci]
|
| 95 |
|
|
# Query all the files for this IP (optional)
|
| 96 |
|
|
#get_files -all -of_objects [get_files *clk_40MHz.xci]
|
| 97 |
|
|
|
| 98 |
|
|
# ----------------------------------------------------------
|
| 99 |
|
|
# finish project initilization
|
| 100 |
|
|
# ----------------------------------------------------------
|
| 101 |
|
|
upgrade_ip [get_ips {clk_40MHz Transceiver_10g_64b67b RX_FIFO TX_FIFO ila_data vio_0} ]
|
| 102 |
|
|
|
| 103 |
|
|
read_xdc -verbose $proj_dir/constraints/core1990_constraints_vc709.xdc
|
| 104 |
|
|
|
| 105 |
|
|
#close [ open $proj_dir/constraints/probes.xdc w ]
|
| 106 |
|
|
#read_xdc -verbose $proj_dir/constraints/probes.xdc
|
| 107 |
|
|
#set_property target_constrs_file $proj_dir/constraints/probes.xdc [current_fileset -constrset]
|
| 108 |
|
|
#set_property STEPS.ROUTE_DESIGN.ARGS.DIRECTIVE MoreGlobalIterations [get_runs impl_1]
|
| 109 |
|
|
|
| 110 |
|
|
|
| 111 |
|
|
set_property top interlaken_wrapper [current_fileset]
|
| 112 |
|
|
|
| 113 |
|
|
#Make this file invalid for simulation, we will replace it with a simulation only file.
|
| 114 |
|
|
|
| 115 |
|
|
set_property SOURCE_SET sources_1 [get_filesets sim_1]
|
| 116 |
|
|
|
| 117 |
|
|
update_compile_order -fileset sim_1
|
| 118 |
|
|
|
| 119 |
|
|
puts "INFO: Done!"
|
