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[/] [core1990_interlaken/] [trunk/] [gateware/] [simulation/] [deframing_burst_tb.vhd] - Blame information for rev 6

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1 6 N.Boukadid
library ieee;
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use ieee.std_logic_1164.all;
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entity testbench_deburster is
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end entity testbench_deburster;
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architecture tb_deburster of testbench_deburster is
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    signal Clk          : std_logic;                     -- Clock input
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        signal Reset            : std_logic;                                     -- Reset decoder
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        signal Data_In      : std_logic_vector(63 downto 0); -- Data input
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        signal Deburst_En   : std_logic;                     -- Enables the decoder
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        signal Data_Out     : std_logic_vector(65 downto 0); -- Decoded 64-bit output
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    signal Data_Control_In  : std_logic;                     -- Indicates whether the word is data or control
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    signal Data_Control_Out : std_logic;                    --    Indicates whether the word is data or control
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    signal CRC24_Error      : std_logic;
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    signal Data_Valid_In    : std_logic;
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    signal Data_Valid_Out   : std_logic;
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    signal FIFO_Full        : std_logic;
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    signal FIFO_Data        : std_logic_vector(4 downto 0);
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    signal FIFO_Write       : std_logic;
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    constant CLK_PERIOD : time := 10 ns;
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begin
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  uut : entity work.Burst_Deframer
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  port map (
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    clk => clk,
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    reset => reset,
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    Deburst_En => Deburst_En,
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    Data_in => Data_in,
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    Data_out => Data_out,
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    Data_control_in => Data_control_in,
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    Data_control_out => Data_control_out,
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    CRC24_Error => CRC24_Error,
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    FIFO_Full => FIFO_Full,
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    FIFO_Data => FIFO_Data,
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    FIFO_Write => FIFO_Write,
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    Data_valid_in => Data_valid_in,
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    Data_valid_out => Data_valid_out
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  );
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   Clk_process :process
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     begin
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          clk <= '1';
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          wait for CLK_PERIOD/2;  --for half of clock period clk stays at '0'.
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          clk <= '0';
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          wait for CLK_PERIOD/2;  --for next half of clock period clk stays at '1'.
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     end process;
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    simulation : process
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    begin
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        wait for 1 ps;
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        Data_control_in <= '0';
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        deburst_en <= '1';
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        reset <= '1';
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        data_in <= (others=>'0');
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        wait for CLK_PERIOD;
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        wait for CLK_PERIOD;
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        reset <= '0';
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        Data_control_in <= '1';
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        Data_in <= X"E000_0001_0000_0000";
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        wait for CLK_PERIOD;
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        Data_control_in <= '0';
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        Data_in <= X"2800_0000_0000_0000";
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        wait for CLK_PERIOD;
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        data_in <= X"1e1e_1e1e_1e1e_1e1e";
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        wait for CLK_PERIOD;
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        Data_in <= X"4f21a2a3a4a5a6a7";
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        wait for CLK_PERIOD;
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        data_in <= X"5f5e5a5c5b60f2a0";
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        wait for CLK_PERIOD;
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        Data_control_in <= '1';
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        data_in  <= X"9000_0001_dd52_35a7";
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        wait for CLK_PERIOD;
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        Data_control_in <= '0';
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        data_in  <= X"70000FFF000000F0";
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        wait for CLK_PERIOD*2;
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        Data_in  <= X"2f5e5d5c5b5a5958";
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        wait for CLK_PERIOD;
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        wait for CLK_PERIOD;
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        Data_Control_In <= '1';
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        data_in  <= X"E000_0001_0000_0000";
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        wait for CLK_PERIOD*3;
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        Data_Control_In <= '0';
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        data_in  <= X"9486576758050505";
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        wait for CLK_PERIOD;
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        data_in <= X"60b35d5dc4a582a7";
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        wait for CLK_PERIOD;
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        Data_control_in <= '1';
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        data_in  <= X"9000_0001_dd52_35a7";
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        wait for CLK_PERIOD;
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        Data_control_in <= '0';
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        data_in <= X"2f5e5d5c5b5a5958";
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        wait for CLK_PERIOD*5;
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        Data_in <= X"1f5e5d5c5b5a5958";
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        wait for CLK_PERIOD*3;
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        Data_Control_In <= '1';
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        Data_in <= X"6400_0000_6222_431a";
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        wait for clk_period;
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        Data_control_in <= '1';
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        Data_in <= X"78f6_78f6_78f6_78f6";
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        wait for CLK_PERIOD;
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        Data_in <= X"2800_0000_0000_0000";
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        wait for CLK_PERIOD;
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        data_in <= X"1e1e_1e1e_1e1e_1e1e";
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        wait for CLK_PERIOD;
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        Data_control_in <= '0';
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        Data_in <= X"4f21a2a3a4a5a6a7";
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        wait for CLK_PERIOD;
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        Data_control_in <= '1';
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        Data_in <= X"E000_0001_0000_0000";
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        wait for CLK_PERIOD;
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        Data_control_in <= '0';
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        data_in <= X"5f5e5a5c5b60f2a0";
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        wait for CLK_PERIOD;
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        data_in <= X"2f5e5d5c5b5a5958";
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        wait for CLK_PERIOD;
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        Data_control_in <= '1';
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        data_in <= X"C000_0001_0000_0000";
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        wait for CLK_PERIOD;
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        Data_control_in <= '0';
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        Data_in <= X"1f5e5d5c5b5a5958";
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        wait for CLK_PERIOD;
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        Data_in <= X"2f5e5d5c5b5a5958";
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        wait for CLK_PERIOD;
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        Data_in <= X"78f6_78f6_78f6_78f6";
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        wait for CLK_PERIOD;
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        Data_control_in <= '1';
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        data_in  <= X"9000_0001_dd52_35a7";
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        wait for CLK_PERIOD;
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        Data_control_in <= '0';
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        Data_in <= X"2800_0000_0000_0000";
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        wait for CLK_PERIOD;
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        data_in <= X"1e1e_1e1e_1e1e_1e1e";
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        wait for CLK_PERIOD;
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        Data_Control_In <= '1';
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        data_in <= X"645e5d5c5b5a5958";
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        wait for CLK_PERIOD;
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        Data_in <= X"78f6_78f6_78f6_78f6";
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        wait for CLK_PERIOD;
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        Data_in <= X"2800_0000_0000_0000";
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        wait for CLK_PERIOD;
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        Data_Control_In <= '0';
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        data_in <= X"1e1e_1e1e_1e1e_1e1e";
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        wait for CLK_PERIOD;
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        Data_in <= X"4f21a2a3a4a5a6a7";
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        wait for CLK_PERIOD;
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        data_in <= X"5f5e5a5c5b60f2a0";
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        wait for CLK_PERIOD;
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        data_in  <= X"635e22a3a4a5a7a7";
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        wait for CLK_PERIOD;
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        data_in <= X"5f5e5a5c5b60f2a0";
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        wait for CLK_PERIOD;
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        data_in  <= X"635e22a3a4a5a7a7";
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        wait for CLK_PERIOD;
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        data_in  <= X"70000FFF000000F0";
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        wait for CLK_PERIOD*2;
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        Data_in <= X"2f5e5d5c5b5a5958";
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        wait for CLK_PERIOD;
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        data_in  <= X"8050505050050505";
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        wait for CLK_PERIOD*3;
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        data_in  <= X"9486576758050505";
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        wait for CLK_PERIOD;
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        data_in <= X"60b35d5dc4a582a7";
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        wait for CLK_PERIOD*60;
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        data_in  <= X"8050505050050505";
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        wait for CLK_PERIOD*3;
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        data_in  <= X"9486576758050505";
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        wait for CLK_PERIOD;
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        data_in <= X"60b35d5dc4a582a7";
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        wait for CLK_PERIOD;
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        data_in <= X"2f5e5d5c5b5a5958";
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        wait for CLK_PERIOD*12;
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        data_in <= X"2c8e5d5c5b5a5958";
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        wait for CLK_PERIOD;
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        Data_in <= X"1f5e5d5c5b5a5958";
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        wait for CLK_PERIOD*26;
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        data_in <= X"2c8e5d5c5b5a5958";
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        wait for CLK_PERIOD*18;
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        data_in <= X"1f5e5d5c5b5a5958";
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        wait for CLK_PERIOD;
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        wait;
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    end process;
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end architecture tb_deburster;
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