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[/] [core1990_interlaken/] [trunk/] [gateware/] [sources/] [interlaken/] [receiver/] [descrambler.vhd] - Blame information for rev 11

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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.ALL;
 
entity Descrambler is
        generic (
                PacketLength : positive
        );
        port (
                Clk                             : in std_logic;                               -- System clock
                Reset                   : in std_logic;                               -- Descrambler reset, use for initialization
 
                Data_In                 : in std_logic_vector (66 downto 0);  -- Data input
                Data_Out                : out std_logic_vector (66 downto 0); -- Data output
 
                Lane_Number             : in std_logic_vector (3 downto 0);   -- Each lane number starts with different scrambler word
                Data_Valid_In   : in std_logic;                       -- 
                Data_Valid_Out  : out std_logic;                      -- Output data is valid for the next component/in lock
                Lock            : out std_logic;
 
        Error_BadSync           : out std_logic;        -- Bad sync words after being in lock
        Error_StateMismatch : out std_logic;    -- Scrambler state mismatches occured more than three times
        Error_NoSync            : out std_logic         -- Bad sync and not been in lock
 
        );
end Descrambler;
 
architecture behavior of Descrambler is
        type state_type is (IDLE, SYNC, LOCKED);
        signal pres_state : state_type;
 
        signal MetaCounter : integer range 0 to PacketLength;
        signal Sync_Word_Detected : std_logic;
        signal Sync_Words : integer range 0 to 3;
        signal ScramblerSyncMismatch : std_logic;
 
        signal Data_Valid_P1, Data_Valid_P2, Data_Valid : std_logic;
        signal Data_P1, Data_Descrambled : std_logic_vector(63 downto 0);
 
        signal Data_In_P1 : std_logic_vector(66 downto 0); ---
        signal scram_state_word_detected : std_logic; ---
 
        signal Scrambler_State_Mismatch : integer range 0 to 3;
    signal Sync_Word_Mismatch : integer range 0 to 4;
 
        signal Poly : std_logic_vector (57 downto 0);
        signal Shiftreg : std_logic_vector (63 downto 0);
        signal Data_HDR_P1, Data_HDR : std_logic_vector(2 downto 0);
        -- Constants
    constant SYNCHRONIZATION : std_logic_vector(63 downto 0) := X"78f6_78f6_78f6_78f6";  -- synchronization framing layer control word
    constant SCRAM_STATE_INIT_VALUE : std_logic_vector(63 downto 0) := X"2800_0000_0000_0000"; -- Starting value of scrambler 
    constant META_TYPE_SYNCHRONIZATION_P: std_logic_vector(4 downto 0) := "11110";
    constant META_TYPE_SCRAM_STATE_P: std_logic_vector(4 downto 0) := "01010";
 
    constant META_TYPE_SYNCHRONIZATION_N: std_logic_vector(4 downto 0) := "00001";
    constant META_TYPE_SCRAM_STATE_N: std_logic_vector(4 downto 0) := "10101";
 
begin
        shiftreg(63) <= Poly(57) xor Poly(38);
    shiftreg(62) <= Poly(56) xor Poly(37);
    shiftreg(61) <= Poly(55) xor Poly(36);
    shiftreg(60) <= Poly(54) xor Poly(35);
    shiftreg(59) <= Poly(53) xor Poly(34);
    shiftreg(58) <= Poly(52) xor Poly(33);
    shiftreg(57) <= Poly(51) xor Poly(32);
    shiftreg(56) <= Poly(50) xor Poly(31);
    shiftreg(55) <= Poly(49) xor Poly(30);
    shiftreg(54) <= Poly(48) xor Poly(29);
    shiftreg(53) <= Poly(47) xor Poly(28);
    shiftreg(52) <= Poly(46) xor Poly(27);
    shiftreg(51) <= Poly(45) xor Poly(26);
    shiftreg(50) <= Poly(44) xor Poly(25);
    shiftreg(49) <= Poly(43) xor Poly(24);
    shiftreg(48) <= Poly(42) xor Poly(23);
    shiftreg(47) <= Poly(41) xor Poly(22);
    shiftreg(46) <= Poly(40) xor Poly(21);
    shiftreg(45) <= Poly(39) xor Poly(20);
    shiftreg(44) <= Poly(38) xor Poly(19);
    shiftreg(43) <= Poly(37) xor Poly(18);
    shiftreg(42) <= Poly(36) xor Poly(17);
    shiftreg(41) <= Poly(35) xor Poly(16);
    shiftreg(40) <= Poly(34) xor Poly(15);
    shiftreg(39) <= Poly(33) xor Poly(14);
    shiftreg(38) <= Poly(32) xor Poly(13);
    shiftreg(37) <= Poly(31) xor Poly(12);
    shiftreg(36) <= Poly(30) xor Poly(11);
    shiftreg(35) <= Poly(29) xor Poly(10);
    shiftreg(34) <= Poly(28) xor Poly(9);
    shiftreg(33) <= Poly(27) xor Poly(8);
    shiftreg(32) <= Poly(26) xor Poly(7);
    shiftreg(31) <= Poly(25) xor Poly(6);
    shiftreg(30) <= Poly(24) xor Poly(5);
    shiftreg(29) <= Poly(23) xor Poly(4);
    shiftreg(28) <= Poly(22) xor Poly(3);
    shiftreg(27) <= Poly(21) xor Poly(2);
    shiftreg(26) <= Poly(20) xor Poly(1);
    shiftreg(25) <= Poly(19) xor Poly(0);
    shiftreg(24) <= Poly(57) xor Poly(38) xor Poly(18);
    shiftreg(23) <= Poly(56) xor Poly(37) xor Poly(17);
    shiftreg(22) <= Poly(55) xor Poly(36) xor Poly(16);
    shiftreg(21) <= Poly(54) xor Poly(35) xor Poly(15);
    shiftreg(20) <= Poly(53) xor Poly(34) xor Poly(14);
    shiftreg(19) <= Poly(52) xor Poly(33) xor Poly(13);
    shiftreg(18) <= Poly(51) xor Poly(32) xor Poly(12);
    shiftreg(17) <= Poly(50) xor Poly(31) xor Poly(11);
    shiftreg(16) <= Poly(49) xor Poly(30) xor Poly(10);
    shiftreg(15) <= Poly(48) xor Poly(29) xor Poly(9);
    shiftreg(14) <= Poly(47) xor Poly(28) xor Poly(8);
    shiftreg(13) <= Poly(46) xor Poly(27) xor Poly(7);
    shiftreg(12) <= Poly(45) xor Poly(26) xor Poly(6);
    shiftreg(11) <= Poly(44) xor Poly(25) xor Poly(5);
    shiftreg(10) <= Poly(43) xor Poly(24) xor Poly(4);
    shiftreg(9) <= Poly(42) xor Poly(23) xor Poly(3);
    shiftreg(8) <= Poly(41) xor Poly(22) xor Poly(2);
    shiftreg(7) <= Poly(40) xor Poly(21) xor Poly(1);
    shiftreg(6) <= Poly(39) xor Poly(20) xor Poly(0);
    shiftreg(5) <= Poly(57) xor Poly(19);
    shiftreg(4) <= Poly(56) xor Poly(18);
    shiftreg(3) <= Poly(55) xor Poly(17);
    shiftreg(2) <= Poly(54) xor Poly(16);
    shiftreg(1) <= Poly(53) xor Poly(15);
    shiftreg(0) <= Poly(52) xor Poly(14);
 
        detection : process (Clk, Reset) is
        begin
                if(Reset = '1') then
            Sync_Word_Detected <= '0';
                elsif (rising_edge(clk)) then
                        if (Data_In(65 downto 64) = "10") and (Data_In(63 downto 0) = SYNCHRONIZATION) then
                                Sync_Word_Detected <= '1';
                        else
                                Sync_Word_Detected <= '0';
                        end if;
                end if;
        end process detection;
 
        data : process (clk, reset) is
    begin
        if (reset = '1') then
            Data_Out <= (others => '0');
        elsif (rising_edge(clk)) then
            Data_Out  <= Data_HDR_P1 & Data_P1;
            Data_Valid_Out <= Data_Valid_P1;
            Data_Valid_P1<= Data_Valid;
        end if;
    end process data;
 
--      state_register : process (clk) is
--    begin
--        if (rising_edge(clk)) then
--            pres_state <= next_state;
--        end if;
--    end process state_register;
 
--    state_decoder : process (pres_state, Sync_Word_Detected, MetaCounter, Sync_words, ScramblerSyncMismatch) is
--    begin
--        case pres_state is
--        when IDLE =>
--                      if(Sync_Word_Detected = '1') then
--                              next_state <= SYNC;
--                      else
--                              next_state <= IDLE;
--                      end if;
--              when SYNC =>
--                      if(Sync_Words = 3 and Sync_Word_Detected = '1') then
--                              next_state <= LOCKED;
--                      elsif(Sync_Words = 0) then
--                              next_state <= IDLE;
--                      else 
--                          next_state <= SYNC;
--                      end if;
--              when LOCKED =>
--                      if(ScramblerSyncMismatch = '1') then
--                              next_state <= IDLE;
--                      else
--                              next_state <= LOCKED;
--                      end if;
--        when others =>
--            next_state <= IDLE;
--        end case;
--    end process state_decoder;
 
    output : process (clk) is
    begin
        if rising_edge(clk) then
            lock <= '0';
            case pres_state is
            when IDLE =>
                Data_P1 <= (others => '0'); -- Reset data registers and polynomial
                Data_Descrambled <= (others => '0');
                                Poly <= (others => '1');
                                Poly(57 downto 54) <= Lane_Number(3 downto 0);
 
                                Error_StateMismatch <= '0'; -- Reset error conditions
                                Error_NoSync <= '0';
                                Error_BadSync <= '0';
 
                                MetaCounter <= 0;           -- Reset other values
                                Data_HDR <= Data_In(66)&"10";
                                Data_HDR_P1 <= Data_In(66)&"10";
 
                                ScramblerSyncMismatch <= '0';
                                Scrambler_State_Mismatch <= 0;
                                Sync_Word_Mismatch <= 0;
                                Data_Valid <= '0';
 
                                if(Sync_Word_Detected = '1') then
                                    MetaCounter <= 1;
                                    Sync_Words <= Sync_Words + 1;
                                    pres_state <= SYNC;
                                end if;
 
                        when SYNC =>
                            if (Data_Valid_In = '1') then
 
                    MetaCounter <= MetaCounter + 1;
                    if(MetaCounter = 0) then
                    --if Data_In(63 downto 0) = SYNCHRONIZATION then
                        if(Sync_Word_Detected = '1') then --First position in metaframe should contain sync
                            Sync_Words <= Sync_Words + 1;
                            if(Sync_Words = 3) then
                                Sync_Words <= 0;
                                Data_Descrambled <= SCRAM_STATE_INIT_VALUE;--X"2800_0000_0000_0000"; 
                                Data_P1 <= SYNCHRONIZATION;
                                Data_HDR <= Data_In(66)&"10";
                                Data_HDR_P1 <= Data_In(66)&"10";
                                Poly <= Data_In(57 downto 0);  -- Scrambler state in poly
                                pres_state <= LOCKED;
                            end if;
                        else
                            Error_NoSync <= '1';
                            pres_state <= IDLE;
                        end if;
                    end if;
 
                    if(MetaCounter = (PacketLength-1)) then
                        MetaCounter <= 0;
                    end if;
                end if;
                if Sync_Words = 0 then
                    pres_state <= IDLE;
                end if;
 
            when LOCKED =>
                Lock <= '1';
                Data_Valid <= '0';
                Data_P1  <= Data_Descrambled;
                Data_HDR_P1  <= Data_HDR;
 
                scram_state_word_detected <= '0';
 
                if (Data_Valid_In = '1') then
                    Data_Valid <= '1';
                    MetaCounter <= MetaCounter + 1;
                    Data_HDR <= Data_In(66 downto 64);
                    --Data_In_P1 <= Data_In; ---
                    if (Data_in(65 downto 64) = "10" and Data_In(63) = '0' and
                        MetaCounter = 0 and
                        ((Data_In(62 downto 58) = META_TYPE_SCRAM_STATE_P ) or
                        (Data_In(62 downto 58) = META_TYPE_SCRAM_STATE_N ))
                        ) then
                        scram_state_word_detected <= '1';
                        Poly <= Data_In(57 downto 0);
                        Data_Descrambled <= Data_In(63 downto 0);
                        if(Data_In(57 downto 0) /= Poly) then
                        --if(Data_In_P1(57 downto 0) /= Poly) then ---
                            Scrambler_State_Mismatch <= Scrambler_State_Mismatch + 1;
                            if(Scrambler_State_Mismatch = 2) then
                                ScramblerSyncMismatch <= '1';
                                Error_StateMismatch <= '1';
                                Scrambler_State_Mismatch <= 0;
                                Sync_Words <= 0;
                                pres_state <= IDLE;
                            end if;
                        end if;
                    elsif (Data_in(65 downto 64) = "10" and Data_In(63) = '0' and
                        Data_In(63 downto 0) = SYNCHRONIZATION ) then
                        --((Data_In(62 downto 58) = META_TYPE_SYNCHRONIZATION_P and Data_In(66) = '0') or 
                        --(Data_In(62 downto 58) = META_TYPE_SYNCHRONIZATION_N and Data_In(66) = '1'))
                        --) then
                        MetaCounter <= 0;
 
                        if(MetaCounter /= (PacketLength-1)) then
                            Sync_Word_Mismatch <= Sync_Word_Mismatch + 1;
                            if(Sync_Word_Mismatch = 3) then
                                Error_BadSync <= '1';
                                Sync_Word_Mismatch <= 0;
                                ScramblerSyncMismatch <= '1';
                                pres_state <= IDLE;
                            end if;
                        end if;
                        Data_Descrambled <= Data_in(63 downto 0);
                    else  -- No Synchronization or scrambler state detected, apply descrambler to data and update Poly
                        Poly <= shiftreg(57 downto 0);
                        Data_Descrambled <= Data_In(63 downto 0) xor (Poly(57 downto 0) & Shiftreg(63 downto 58));
                    end if;
 
 
 
                end if;
            when others =>
                pres_state <= IDLE;
            end case;
        end if;
    end process output;
 
end architecture behavior;

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[/] [core1990_interlaken/] [trunk/] [gateware/] [sources/] [interlaken/] [receiver/] [descrambler.vhd] - Blame information for rev 11

Line No.	Rev	Author	Line
1	11	N.Boukadid	`library ieee;`
2			`use ieee.std_logic_1164.all;`
3			`use ieee.std_logic_unsigned.all;`
4			`use ieee.numeric_std.ALL;`
5
6			`entity Descrambler is`
7			`generic (`
8			`PacketLength : positive`
9			`);`
10			`port (`
11			`Clk : in std_logic; -- System clock`
12			`Reset : in std_logic; -- Descrambler reset, use for initialization`
13
14			`Data_In : in std_logic_vector (66 downto 0); -- Data input`
15			`Data_Out : out std_logic_vector (66 downto 0); -- Data output`
16
17			`Lane_Number : in std_logic_vector (3 downto 0); -- Each lane number starts with different scrambler word`
18			`Data_Valid_In : in std_logic; --`
19			`Data_Valid_Out : out std_logic; -- Output data is valid for the next component/in lock`
20			`Lock : out std_logic;`
21
22			`Error_BadSync : out std_logic; -- Bad sync words after being in lock`
23			`Error_StateMismatch : out std_logic; -- Scrambler state mismatches occured more than three times`
24			`Error_NoSync : out std_logic -- Bad sync and not been in lock`
25
26			`);`
27			`end Descrambler;`
28
29			`architecture behavior of Descrambler is`
30			`type state_type is (IDLE, SYNC, LOCKED);`
31			`signal pres_state : state_type;`
32
33			`signal MetaCounter : integer range 0 to PacketLength;`
34			`signal Sync_Word_Detected : std_logic;`
35			`signal Sync_Words : integer range 0 to 3;`
36			`signal ScramblerSyncMismatch : std_logic;`
37
38			`signal Data_Valid_P1, Data_Valid_P2, Data_Valid : std_logic;`
39			`signal Data_P1, Data_Descrambled : std_logic_vector(63 downto 0);`
40
41			`signal Data_In_P1 : std_logic_vector(66 downto 0); ---`
42			`signal scram_state_word_detected : std_logic; ---`
43
44			`signal Scrambler_State_Mismatch : integer range 0 to 3;`
45			`signal Sync_Word_Mismatch : integer range 0 to 4;`
46
47			`signal Poly : std_logic_vector (57 downto 0);`
48			`signal Shiftreg : std_logic_vector (63 downto 0);`
49			`signal Data_HDR_P1, Data_HDR : std_logic_vector(2 downto 0);`
50			`-- Constants`
51			`constant SYNCHRONIZATION : std_logic_vector(63 downto 0) := X"78f6_78f6_78f6_78f6"; -- synchronization framing layer control word`
52			`constant SCRAM_STATE_INIT_VALUE : std_logic_vector(63 downto 0) := X"2800_0000_0000_0000"; -- Starting value of scrambler`
53			`constant META_TYPE_SYNCHRONIZATION_P: std_logic_vector(4 downto 0) := "11110";`
54			`constant META_TYPE_SCRAM_STATE_P: std_logic_vector(4 downto 0) := "01010";`
55
56			`constant META_TYPE_SYNCHRONIZATION_N: std_logic_vector(4 downto 0) := "00001";`
57			`constant META_TYPE_SCRAM_STATE_N: std_logic_vector(4 downto 0) := "10101";`
58
59			`begin`
60			`shiftreg(63) <= Poly(57) xor Poly(38);`
61			`shiftreg(62) <= Poly(56) xor Poly(37);`
62			`shiftreg(61) <= Poly(55) xor Poly(36);`
63			`shiftreg(60) <= Poly(54) xor Poly(35);`
64			`shiftreg(59) <= Poly(53) xor Poly(34);`
65			`shiftreg(58) <= Poly(52) xor Poly(33);`
66			`shiftreg(57) <= Poly(51) xor Poly(32);`
67			`shiftreg(56) <= Poly(50) xor Poly(31);`
68			`shiftreg(55) <= Poly(49) xor Poly(30);`
69			`shiftreg(54) <= Poly(48) xor Poly(29);`
70			`shiftreg(53) <= Poly(47) xor Poly(28);`
71			`shiftreg(52) <= Poly(46) xor Poly(27);`
72			`shiftreg(51) <= Poly(45) xor Poly(26);`
73			`shiftreg(50) <= Poly(44) xor Poly(25);`
74			`shiftreg(49) <= Poly(43) xor Poly(24);`
75			`shiftreg(48) <= Poly(42) xor Poly(23);`
76			`shiftreg(47) <= Poly(41) xor Poly(22);`
77			`shiftreg(46) <= Poly(40) xor Poly(21);`
78			`shiftreg(45) <= Poly(39) xor Poly(20);`
79			`shiftreg(44) <= Poly(38) xor Poly(19);`
80			`shiftreg(43) <= Poly(37) xor Poly(18);`
81			`shiftreg(42) <= Poly(36) xor Poly(17);`
82			`shiftreg(41) <= Poly(35) xor Poly(16);`
83			`shiftreg(40) <= Poly(34) xor Poly(15);`
84			`shiftreg(39) <= Poly(33) xor Poly(14);`
85			`shiftreg(38) <= Poly(32) xor Poly(13);`
86			`shiftreg(37) <= Poly(31) xor Poly(12);`
87			`shiftreg(36) <= Poly(30) xor Poly(11);`
88			`shiftreg(35) <= Poly(29) xor Poly(10);`
89			`shiftreg(34) <= Poly(28) xor Poly(9);`
90			`shiftreg(33) <= Poly(27) xor Poly(8);`
91			`shiftreg(32) <= Poly(26) xor Poly(7);`
92			`shiftreg(31) <= Poly(25) xor Poly(6);`
93			`shiftreg(30) <= Poly(24) xor Poly(5);`
94			`shiftreg(29) <= Poly(23) xor Poly(4);`
95			`shiftreg(28) <= Poly(22) xor Poly(3);`
96			`shiftreg(27) <= Poly(21) xor Poly(2);`
97			`shiftreg(26) <= Poly(20) xor Poly(1);`
98			`shiftreg(25) <= Poly(19) xor Poly(0);`
99			`shiftreg(24) <= Poly(57) xor Poly(38) xor Poly(18);`
100			`shiftreg(23) <= Poly(56) xor Poly(37) xor Poly(17);`
101			`shiftreg(22) <= Poly(55) xor Poly(36) xor Poly(16);`
102			`shiftreg(21) <= Poly(54) xor Poly(35) xor Poly(15);`
103			`shiftreg(20) <= Poly(53) xor Poly(34) xor Poly(14);`
104			`shiftreg(19) <= Poly(52) xor Poly(33) xor Poly(13);`
105			`shiftreg(18) <= Poly(51) xor Poly(32) xor Poly(12);`
106			`shiftreg(17) <= Poly(50) xor Poly(31) xor Poly(11);`
107			`shiftreg(16) <= Poly(49) xor Poly(30) xor Poly(10);`
108			`shiftreg(15) <= Poly(48) xor Poly(29) xor Poly(9);`
109			`shiftreg(14) <= Poly(47) xor Poly(28) xor Poly(8);`
110			`shiftreg(13) <= Poly(46) xor Poly(27) xor Poly(7);`
111			`shiftreg(12) <= Poly(45) xor Poly(26) xor Poly(6);`
112			`shiftreg(11) <= Poly(44) xor Poly(25) xor Poly(5);`
113			`shiftreg(10) <= Poly(43) xor Poly(24) xor Poly(4);`
114			`shiftreg(9) <= Poly(42) xor Poly(23) xor Poly(3);`
115			`shiftreg(8) <= Poly(41) xor Poly(22) xor Poly(2);`
116			`shiftreg(7) <= Poly(40) xor Poly(21) xor Poly(1);`
117			`shiftreg(6) <= Poly(39) xor Poly(20) xor Poly(0);`
118			`shiftreg(5) <= Poly(57) xor Poly(19);`
119			`shiftreg(4) <= Poly(56) xor Poly(18);`
120			`shiftreg(3) <= Poly(55) xor Poly(17);`
121			`shiftreg(2) <= Poly(54) xor Poly(16);`
122			`shiftreg(1) <= Poly(53) xor Poly(15);`
123			`shiftreg(0) <= Poly(52) xor Poly(14);`
124
125			`detection : process (Clk, Reset) is`
126			`begin`
127			`if(Reset = '1') then`
128			`Sync_Word_Detected <= '0';`
129			`elsif (rising_edge(clk)) then`
130			`if (Data_In(65 downto 64) = "10") and (Data_In(63 downto 0) = SYNCHRONIZATION) then`
131			`Sync_Word_Detected <= '1';`
132			`else`
133			`Sync_Word_Detected <= '0';`
134			`end if;`
135			`end if;`
136			`end process detection;`
137
138			`data : process (clk, reset) is`
139			`begin`
140			`if (reset = '1') then`
141			`Data_Out <= (others => '0');`
142			`elsif (rising_edge(clk)) then`
143			`Data_Out <= Data_HDR_P1 & Data_P1;`
144			`Data_Valid_Out <= Data_Valid_P1;`
145			`Data_Valid_P1<= Data_Valid;`
146			`end if;`
147			`end process data;`
148
149			`-- state_register : process (clk) is`
150			`-- begin`
151			`-- if (rising_edge(clk)) then`
152			`-- pres_state <= next_state;`
153			`-- end if;`
154			`-- end process state_register;`
155
156			`-- state_decoder : process (pres_state, Sync_Word_Detected, MetaCounter, Sync_words, ScramblerSyncMismatch) is`
157			`-- begin`
158			`-- case pres_state is`
159			`-- when IDLE =>`
160			`-- if(Sync_Word_Detected = '1') then`
161			`-- next_state <= SYNC;`
162			`-- else`
163			`-- next_state <= IDLE;`
164			`-- end if;`
165			`-- when SYNC =>`
166			`-- if(Sync_Words = 3 and Sync_Word_Detected = '1') then`
167			`-- next_state <= LOCKED;`
168			`-- elsif(Sync_Words = 0) then`
169			`-- next_state <= IDLE;`
170			`-- else`
171			`-- next_state <= SYNC;`
172			`-- end if;`
173			`-- when LOCKED =>`
174			`-- if(ScramblerSyncMismatch = '1') then`
175			`-- next_state <= IDLE;`
176			`-- else`
177			`-- next_state <= LOCKED;`
178			`-- end if;`
179			`-- when others =>`
180			`-- next_state <= IDLE;`
181			`-- end case;`
182			`-- end process state_decoder;`
183
184			`output : process (clk) is`
185			`begin`
186			`if rising_edge(clk) then`
187			`lock <= '0';`
188			`case pres_state is`
189			`when IDLE =>`
190			`Data_P1 <= (others => '0'); -- Reset data registers and polynomial`
191			`Data_Descrambled <= (others => '0');`
192			`Poly <= (others => '1');`
193			`Poly(57 downto 54) <= Lane_Number(3 downto 0);`
194
195			`Error_StateMismatch <= '0'; -- Reset error conditions`
196			`Error_NoSync <= '0';`
197			`Error_BadSync <= '0';`
198
199			`MetaCounter <= 0; -- Reset other values`
200			`Data_HDR <= Data_In(66)&"10";`
201			`Data_HDR_P1 <= Data_In(66)&"10";`
202
203			`ScramblerSyncMismatch <= '0';`
204			`Scrambler_State_Mismatch <= 0;`
205			`Sync_Word_Mismatch <= 0;`
206			`Data_Valid <= '0';`
207
208			`if(Sync_Word_Detected = '1') then`
209			`MetaCounter <= 1;`
210			`Sync_Words <= Sync_Words + 1;`
211			`pres_state <= SYNC;`
212			`end if;`
213
214			`when SYNC =>`
215			`if (Data_Valid_In = '1') then`
216
217			`MetaCounter <= MetaCounter + 1;`
218			`if(MetaCounter = 0) then`
219			`--if Data_In(63 downto 0) = SYNCHRONIZATION then`
220			`if(Sync_Word_Detected = '1') then --First position in metaframe should contain sync`
221			`Sync_Words <= Sync_Words + 1;`
222			`if(Sync_Words = 3) then`
223			`Sync_Words <= 0;`
224			`Data_Descrambled <= SCRAM_STATE_INIT_VALUE;--X"2800_0000_0000_0000";`
225			`Data_P1 <= SYNCHRONIZATION;`
226			`Data_HDR <= Data_In(66)&"10";`
227			`Data_HDR_P1 <= Data_In(66)&"10";`
228			`Poly <= Data_In(57 downto 0); -- Scrambler state in poly`
229			`pres_state <= LOCKED;`
230			`end if;`
231			`else`
232			`Error_NoSync <= '1';`
233			`pres_state <= IDLE;`
234			`end if;`
235			`end if;`
236
237			`if(MetaCounter = (PacketLength-1)) then`
238			`MetaCounter <= 0;`
239			`end if;`
240			`end if;`
241			`if Sync_Words = 0 then`
242			`pres_state <= IDLE;`
243			`end if;`
244
245			`when LOCKED =>`
246			`Lock <= '1';`
247			`Data_Valid <= '0';`
248			`Data_P1 <= Data_Descrambled;`
249			`Data_HDR_P1 <= Data_HDR;`
250
251			`scram_state_word_detected <= '0';`
252
253			`if (Data_Valid_In = '1') then`
254			`Data_Valid <= '1';`
255			`MetaCounter <= MetaCounter + 1;`
256			`Data_HDR <= Data_In(66 downto 64);`
257			`--Data_In_P1 <= Data_In; ---`
258			`if (Data_in(65 downto 64) = "10" and Data_In(63) = '0' and`
259			`MetaCounter = 0 and`
260			`((Data_In(62 downto 58) = META_TYPE_SCRAM_STATE_P ) or`
261			`(Data_In(62 downto 58) = META_TYPE_SCRAM_STATE_N ))`
262			`) then`
263			`scram_state_word_detected <= '1';`
264			`Poly <= Data_In(57 downto 0);`
265			`Data_Descrambled <= Data_In(63 downto 0);`
266			`if(Data_In(57 downto 0) /= Poly) then`
267			`--if(Data_In_P1(57 downto 0) /= Poly) then ---`
268			`Scrambler_State_Mismatch <= Scrambler_State_Mismatch + 1;`
269			`if(Scrambler_State_Mismatch = 2) then`
270			`ScramblerSyncMismatch <= '1';`
271			`Error_StateMismatch <= '1';`
272			`Scrambler_State_Mismatch <= 0;`
273			`Sync_Words <= 0;`
274			`pres_state <= IDLE;`
275			`end if;`
276			`end if;`
277			`elsif (Data_in(65 downto 64) = "10" and Data_In(63) = '0' and`
278			`Data_In(63 downto 0) = SYNCHRONIZATION ) then`
279			`--((Data_In(62 downto 58) = META_TYPE_SYNCHRONIZATION_P and Data_In(66) = '0') or`
280			`--(Data_In(62 downto 58) = META_TYPE_SYNCHRONIZATION_N and Data_In(66) = '1'))`
281			`--) then`
282			`MetaCounter <= 0;`
283
284			`if(MetaCounter /= (PacketLength-1)) then`
285			`Sync_Word_Mismatch <= Sync_Word_Mismatch + 1;`
286			`if(Sync_Word_Mismatch = 3) then`
287			`Error_BadSync <= '1';`
288			`Sync_Word_Mismatch <= 0;`
289			`ScramblerSyncMismatch <= '1';`
290			`pres_state <= IDLE;`
291			`end if;`
292			`end if;`
293			`Data_Descrambled <= Data_in(63 downto 0);`
294			`else -- No Synchronization or scrambler state detected, apply descrambler to data and update Poly`
295			`Poly <= shiftreg(57 downto 0);`
296			`Data_Descrambled <= Data_In(63 downto 0) xor (Poly(57 downto 0) & Shiftreg(63 downto 58));`
297			`end if;`
298
299
300
301			`end if;`
302			`when others =>`
303			`pres_state <= IDLE;`
304			`end case;`
305			`end if;`
306			`end process output;`
307
308			`end architecture behavior;`