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[/] [core1990_interlaken/] [trunk/] [gateware/] [sources/] [interlaken/] [test/] [data_generator.vhd] - Blame information for rev 11

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1 11 N.Boukadid
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.numeric_std.ALL;
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library work;
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entity data_generator is
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        port (
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            clk           : in std_logic;
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            Packet_Length : in std_logic_vector(6 downto 0);
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            TX_FIFO_Full  : in std_logic;
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            data_out      : out std_logic_vector(63 downto 0);
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        sop               : out std_logic;
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        eop               : out std_logic;
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        eop_valid         : out std_logic_vector(2 downto 0);
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        channel           : out std_logic_vector(7 downto 0);
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            write_enable  : out std_logic
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        );
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end entity data_generator;
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architecture rtl of data_generator is
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        signal counter : integer range 0 to 512;
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    signal data : std_logic_vector(63 downto 0):=(others => '0');
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begin
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    data_proc : process(clk)
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    begin
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                if rising_edge(clk) then
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                    if(TX_FIFO_Full = '0') then
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                                sop <= '0';
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                eop <= '0';
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                                eop_valid <= "000";
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                                counter <= counter + 1;
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                                channel <= X"01";
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                                if (counter = 0 ) then
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                                        sop <= '1';
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                                elsif (counter = to_integer(unsigned(Packet_Length))) then
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                                        counter <= 0;
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                                        eop <= '1';
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                                        eop_valid <= "111";
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                                end if;
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                                data <= data+1;
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                        end if;
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                end if;
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    end process;
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    write_enable <= not TX_FIFO_Full;
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    data_out <= data;
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end architecture rtl;

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