OpenCores
URL https://opencores.org/ocsvn/core1990_interlaken/core1990_interlaken/trunk

Subversion Repositories core1990_interlaken

[/] [core1990_interlaken/] [trunk/] [gateware/] [sources/] [interlaken/] [test/] [pipeline.vhd] - Blame information for rev 11

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 11 N.Boukadid
library ieee;
2
use ieee.std_logic_1164.all;
3
use ieee.std_logic_unsigned.all;
4
use ieee.numeric_std.ALL;
5
library work;
6
 
7
entity pipe is
8
    generic (
9
                Nmax : integer
10
                );
11
        port (
12
            N : in  std_logic_vector(6 downto 0);
13
            pipe_in: in std_logic_vector(68 downto 0);
14
            pipe_out: out std_logic_vector(68 downto 0);
15
            clk: in std_logic
16
        );
17
end entity pipe;
18
 
19
architecture rtl of pipe is
20
    type slv64_array is array (natural range <>) of std_logic_vector(68 downto 0);
21
    signal pipeline : slv64_array (0 to Nmax);
22
begin
23
 
24
    pipe_proc: process(clk, pipe_in, pipeline, N)
25
    begin
26
        pipeline(0) <= pipe_in;
27
                if rising_edge(clk) then
28
                        for i in 1 to Nmax loop
29
                                pipeline(i) <= pipeline(i-1);
30
                        end loop;
31
                end if;
32
                pipe_out <= pipeline(to_integer(unsigned(N)));
33
    end process;
34
 
35
end architecture rtl;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.