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[/] [core1990_interlaken/] [trunk/] [gateware/] [sources/] [interlaken/] [transmitter/] [encoder.vhd] - Blame information for rev 11

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1 11 N.Boukadid
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity Encoder is
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    port(
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        Clk          : in std_logic;                     -- Clock input
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        Data_In      : in std_logic_vector(66 downto 0); -- Data input
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        Data_Out     : out std_logic_vector(66 downto 0);-- Encoded 67-bit output
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        --Data_Control : in std_logic;                     -- Determines whether the word is data or control
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        Data_valid_in: in std_logic;
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        Data_valid_out: out std_logic;
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        Encoder_En   : in std_logic;                     -- Enables the encoder
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        Encoder_Rst  : in std_logic;                     -- Resets the encoder
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        --Offset       : out std_logic_vector(7 downto 0); -- Test to see the average values of ones and zeros
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        Gearboxready : in std_logic
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    );
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end Encoder;
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architecture Encoding of Encoder is
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begin
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    output : process (clk, Encoder_Rst)
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        variable Data_Temp : std_logic_vector(66 downto 0) := (others => '0');
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                variable Disparity_Data : integer := 0; -- Disparity of 64 bit data. Inversion bit has to be added at the end.
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        variable Offset_V : integer := 32;
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        variable Disparity_Running : integer;
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        begin
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        if (Encoder_Rst = '1') then
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            Data_Out    <= (others => '0');
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            Data_Temp   := (others => '0');
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            --Offset      <= (others => '0');
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        elsif (rising_edge(clk)) then
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            if (encoder_en = '1' and Gearboxready = '1') then
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                Data_Temp(63 downto 0) := Data_In(63 downto 0);
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                Disparity_Data := 0;  -- Calculating disparity of incoming data
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                for i in 63 downto 0 loop
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                    if Data_In(i) = '1' then
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                        Disparity_Data := Disparity_Data + 1;
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                    end if;
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                end loop;
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                Data_Temp(66) := '0'; -- Determine inversion
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                if(Disparity_Running >= 32) then
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                    if (Disparity_Data >= 32) then
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                        Data_Temp(63 downto 0) := not(Data_Temp(63 downto 0));
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                        Data_Temp(66) := '1';
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                    end if;
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                else
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                    if (Disparity_Data < 32) then
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                        Data_Temp(63 downto 0) := not(Data_Temp(63 downto 0));
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                        Data_Temp(66) := '1';
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                    end if;
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                end if;
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                Data_Temp(65 downto 64) := Data_in(65 downto 64); -- Control ("10") / data word ("01")
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                --------------------------------------------
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--                Offset_V := 32;       -- Debug to see average transmitted disparity
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--                for j in 63 downto 0 loop
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--                    if (Data_Temp(j) = '1') then
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--                        Offset_V := Offset_V + 1;
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--                    else
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--                        Offset_V := Offset_V - 1;
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--                    end if;
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--                end loop;
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--                Offset <= std_logic_vector(to_unsigned(Offset_V, Offset'length));
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                --------------------------------------------
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                Disparity_Running := 0; -- Measure disparity in transmitted word
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                for j in 63 downto 0 loop
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                    if (Data_Temp(j) = '1') then
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                        Disparity_Running := Disparity_Running + 1;
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                    end if;
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                end loop;
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                Data_Out <= Data_Temp;
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                Data_valid_out <= Data_valid_in;
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            end if;
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        end if;
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    end process output;
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end architecture Encoding;

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