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[/] [core1990_interlaken/] [trunk/] [gateware/] [sources/] [interlaken/] [transmitter/] [framing_burst.vhd] - Blame information for rev 11

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library ieee;
use ieee.std_logic_1164.all;
 
entity Burst_Framer is
        generic (
        BurstMax   : positive;      -- Configurable value of BurstMax
        BurstShort : positive       -- Configurable value of BurstShort
        );
        port (
                clk       : in std_logic;                                             -- System clock
                reset : in std_logic;                                         -- Reset, use for initialization
 
                TX_Enable     : in std_logic;                         -- Enable the TX
                TX_SOP        : in std_logic;                         -- Start of Packet
                TX_ValidBytes : in std_logic_vector(2 downto 0);      -- Valid bytes packet contains
                TX_EOP        : in std_logic;                         -- End of Packet
                TX_Channel    : in std_logic_vector(7 downto 0);      -- Select transmit channel (yet unutilized)
 
                Data_in          : in std_logic_vector(63 downto 0);  -- Input data
                Data_in_valid    : in std_logic ;                     -- 1 means that the fifo data was successfully read
                Data_out         : out std_logic_vector(66 downto 0); -- To scrambling/framing
                Data_valid_out   : out std_logic;                                     -- Indicate data transmitted is valid
                --Data_control_out : out std_logic;                     -- Control word indication
 
            HealthLane       : out std_logic;                      -- Lane status bit transmitted for diagnostic word
        HealthInterface  : out std_logic;                      -- Interface status bit transmitted for diagnostic word
 
        TX_FlowControl  : in std_logic_vector(15 downto 0);     -- Flow control data (yet unutilized)
        RX_prog_full    : in std_logic_vector(15 downto 0);
 
        FIFO_Empty   : in std_logic;
 
                FIFO_meta    : in std_logic;                          -- Request from the MetaFraming to read data from the FIFO
                FIFO_data    : in std_logic_vector(4 downto 0);       -- Determines how many bytes have to be transmitted (yet unutilized)
                FIFO_read    : out std_logic;                                     -- Request data from the FIFO
                Gearboxready : in std_logic
        );
end Burst_Framer;
 
architecture framing of Burst_Framer is
        type state_type is (IDLE, DATA, WORD, FILL, EOP_SET, EOP_FULL, EOP_EMPTY);
        signal pres_state, next_state : state_type;
 
        signal Data_Temp             : std_logic_vector(66 downto 0) := (others => '0');
        signal Byte_Counter          : integer range 0 to 80;
        signal Word_Control_out      : std_logic;
        signal Data_Control          : std_logic;
        signal Data_Valid            : std_logic := '0';
        signal FIFO_readreq          : std_logic;
        signal Word_valid_out        : std_logic;
        signal HDR_P1, HDR_P2 : std_logic_vector(2 downto 0);
        signal Valid_P1, Valid_P2 : std_logic
        ;
 
        signal Data_P1, Data_P2                    : std_logic_vector(63 downto 0);    -- Pipelined data
        --signal ControlValid_P1, ControlValid_P2    : std_logic_vector(1 downto 0);     -- Pipelined control/valid indicator
        signal Data_valid_temp : std_logic;
        signal valid_temp : std_logic := '0';
 
    signal CRC24_TX  : std_logic_vector(66 downto 0) := (others => '0');   -- Data transmitted to CRC-24
    signal CRC24_Out : std_logic_vector(23 downto 0);   -- Calculated CRC-24 which returns
    signal CRC24_En  : std_logic;             --l          -- Indicate the CRC-24 the data is valid
    signal CRC24_RST : std_logic;                       -- CRC24 reset
    signal CRC24_P1  : std_logic;                       -- CRC24 reset pipelining
    --signal CRC24_RST_P1  : std_logic;                       -- CRC24 reset pipelining
    signal CRC24_Stored : std_logic_vector(31 downto 0);
    signal CRC24_Ready : std_logic;
    signal CRC_P1, CRC_P2 : std_logic;
 
    signal Gearboxready_P1 : std_logic;
    signal CalcCrc   : std_logic;                       -- CRC24_EN and Gearboxready
    signal TX_ValidBytes_s : std_logic_vector(2 downto 0);
 
        -- Constants
   -- constant SOP : std_logic_vector(2 downto 0) := "100";  -- Start Of Packet
   -- constant EOP : std_logic_vector(2 downto 0) := "001";  -- End Of Pack
 
 
 
begin
 
        CRC_24_Encoding : entity work.CRC_24 -- Define the connections of the CRC-24 component to the Burst component and generics
        --generic map
        --(
    --    Nbits       => 64,
    --    CRC_Width   => 24,
    --    G_Poly      => X"32_8B63", --Test with CRC-32 : 1EDC_6F41 (Interlaken-24 : X"32_8B63") previous: 04C11DB7
    --    G_InitVal   => X"FF_FFFF"
        --)
    port map
        (
        Clk     => Clk,
        DIn     => CRC24_TX(63 downto 0),
        CRC     => CRC24_Out,
        Calc    => CalcCrc,
        Reset   => CRC24_RST
        );
 
    CalcCrc <= Gearboxready and FIFO_meta;
 
 
    pipeline : process (clk, reset)
        variable CRC24_Out_v: std_logic_vector(23 downto 0);
        variable Data_valid_check : std_logic;
        begin
        if (reset = '1') then
            Data_P1          <= (others => '0');
            Data_P2          <= (others => '0');
            Data_out         <= (others => '0');
            CRC24_Stored     <= (others => '0');
            --ControlValid_P1  <= "00";
            --ControlValid_P2  <= "00";
            --Data_Control_Out <= '0';
            Data_Valid_Out   <= '0';
            CRC24_Ready      <= '0';
            --CRC24_RST_P1     <= '0';
        elsif (rising_edge(clk)) then
--            if (CRC24_Rst <= '1') then
--                CRC24_PP1 <= '1';
--            else
--                CRC24_PP1 <= CRC24_PP1;
--            end if;
            --CRC24_PP1 <= CRC24_PP1;
            --Data_control_out <= '0';
 
--            if(CRC24_Rst_P1 = '1' and (Data_P2(62 downto 60) = "100" or Data_P2(61 downto 60) = "01")) then
--                CRC24_Out_v := CRC24_Out;
--            end if;
 
            Data_Valid_Out <= '0';
            CRC_P1 <= '0';
 
            Gearboxready_P1 <= Gearboxready;
            --CRC24_Rst_P1 <= CRC24_Rst;
 
            if(CRC24_TX(62 downto 60) = "100" or CRC24_TX(61 downto 60) = "01") then
                CRC_P1 <= '1';
            end if;
            CRC_P2 <= CRC_P1;
 
            if (CRC_P2 = '1') then
                CRC24_Out_v := CRC24_Out;
            end if;
 
            if(Gearboxready = '1' and FIFO_meta = '1') then
                Data_P1  <= CRC24_TX(63 downto 0);
                Data_P2  <= Data_P1;
                Data_out(63 downto 0) <= Data_P2;
 
                HDR_P1 <= CRC24_TX(66 downto 64);
                HDR_P2  <= HDR_P1;
                Data_Out(66 downto 64) <= HDR_P2;
 
                Valid_P1  <= Data_Valid;
                Valid_P2 <= Valid_P1;
                Data_Valid_Out   <= Valid_P2;
                Data_valid_check := Valid_P2;
 
                --if(HDR_P2 = "010"and(Data_P2(62 downto 60) = "110" or Data_P2(61 downto 60) = "01")) then --Control word BurstMax or EOP only word 
                if(HDR_P2 = "010"and(Data_P2(61 downto 60) = "01")) then --Control word BurstMax or EOP only word 
                    Data_out(23 downto 0) <= CRC24_Out_v; -- Include CRC in last packet of burst   
                end if;
 
                if(Valid_P2 = '0') then
                    Data_Out <= "010"&X"8000_0001_0000_0000";  -- Idle control word
                end if;
 
                --CRC24_PP1 <= CRC24_Rst;
            end if;
 
            if(Data_valid_check = '0') then
                Data_Out <= "010"&X"8000_0001_0000_0000";  -- Idle control word
            end if;
 
--            CRC24_RST_P1 <= CRC24_Rst;
 
--            if (CRC24_RST_P1 = '1') then 
--               if(ControlValid_P2(1) = '1' and Gearboxready = '1' and FIFO_meta = '1' and CRC24_Ready = '0') then
--                   Data_out(31 downto 0) <= CRC24_Out; -- Include CRC in last packet of burst
--               else
--                   if (CRC24_Ready = '0') then
--                       CRC24_Stored <= CRC24_Out;
--                       CRC24_Ready <= '1';
--                   end if;
--               end if;
--            end if;
 
--            if (CRC24_Ready = '1' and ControlValid_P2(1) = '1' and Gearboxready = '1' and FIFO_meta = '1') then
--               Data_out(31 downto 0) <= CRC24_Stored;
--               CRC24_Ready <= '0';
--            end if;              
 
        end if;
        end process pipeline;
 
--      valid : process(FIFO_meta, Gearboxready, data_in_valid)
--      begin
--         --if(rising_edge(clk)) then
--             if(Gearboxready = '0' or FIFO_meta = '0') and data_in_valid = '1' then
--                 valid_temp <= '1';
--             end if;
--      -- end if;
--      end process valid;
 
        fifo_reading : process (FIFO_meta, FIFO_readreq, Gearboxready, FIFO_Empty) is
        begin
           if (FIFO_meta = '1' and FIFO_readreq = '1' and Gearboxready = '1' and FIFO_Empty = '0') then
               FIFO_read <= '1';
           else
               FIFO_read <= '0';
           end if;
        end process fifo_reading;
 
        state_register : process (clk) is -- Determines the next state of the FSM
        begin
                if (rising_edge(clk)) then
            pres_state <= next_state;
            if TX_EOP = '1' then
                TX_ValidBytes_s <= TX_ValidBytes;
            end if;
                end if;
        end process state_register;
 
        state_decoder : process (pres_state, TX_SOP, TX_Enable, TX_EOP, Byte_Counter, FIFO_meta, Gearboxready) is
        begin
            if(Gearboxready = '0' or FIFO_meta = '0') then
               next_state <= pres_state;
            else
            case pres_state is
            when IDLE =>
                if (TX_Enable = '1' and TX_SOP = '1' and TX_EOP = '0') then
                    next_state <= DATA;
                elsif (TX_Enable = '1' and TX_SOP = '1' and TX_EOP = '1') then
                    next_state <= EOP_SET;
                else
                    next_state <= IDLE;
                end if;
            when DATA =>
                if(TX_EOP = '1' ) then
                    next_state <= EOP_SET;
                elsif (Byte_Counter >= (BurstMax-8)) then
                    next_state <= WORD;
                else
                    next_state <= DATA;
                end if;
            when WORD =>
                next_state <= DATA;
            when EOP_SET =>
                if (Byte_Counter >= BurstShort) then
                    next_state <= EOP_FULL;
                else
                    next_state <= EOP_EMPTY;
                end if;
            when EOP_EMPTY =>
                if (Byte_Counter >= BurstShort) then
                   next_state <= IDLE;
                else
                   next_state <= FILL;
                end if;
            when FILL =>
                if (Byte_Counter >= BurstShort-8) then
                    next_state <= IDLE;
                else
                    next_state <= FILL;
                end if;
            when EOP_FULL =>
                next_state <= IDLE;
            when others =>
                next_state <= IDLE;
            end case;
        end if;
        end process state_decoder;
 
        output : process (pres_state, clk) is
        begin
        if rising_edge(clk) then
            CRC24_RST <= '0';
            -- X"Type/SOP/EOP(2)FlowC(2)_FlowC(2)Channel(2)_Mutiple(2)CRC24(2)_CRC24(2)CRC24(2)" Structure of packet
            if(Gearboxready = '1' and  FIFO_meta = '1' ) then
                case pres_state is
                when IDLE =>            -- Wait for SOP, start reading FIFO and save last cycle data
                    CRC24_EN <= '0'; -- Reset CRC calculations
                    CRC24_RST <= '1';
                    Data_Valid <= '0';
                    Word_Control_out <= '0';
                    FIFO_readreq <= '1';
                    Byte_Counter <= 8;
                    CRC24_P1 <= '0';
                    Data_Control <= '0';
                    valid_temp <= '0';
 
                    Data_temp <= "001"&Data_in;
                    Data_valid_temp <= Data_in_valid;
 
                    if (TX_SOP = '1' and TX_Enable = '1') then -- Indicates the start of data flow
                        CRC24_TX <= "010"&X"E000_0001_0000_0000"; -- Start packet E000_0001_0000_0000
                        --CRC24_TX(55 downto 40) <= RX_prog_full;
                        Data_Valid <= '1';
                        Data_valid_temp <= '1'; --Start of a new packet is always valid
                   -- elsif (TX_flowcontrol(0) = '0') then  -- TODO Flowcontrol is not used? why as condition? 
                    --    CRC24_TX <= "010"&X"C000_0001_0000_0000"; --  C000_0001_0000_0000
                     --   CRC24_TX(55 downto 40) <= RX_prog_full;
 
                    else
                        CRC24_TX <= "001"&X"0000_0000_0000_0000"; -- data word placeholder
                    end if;
 
                    if(TX_EOP = '1' and TX_SOP = '1') then
                        FIFO_readreq <= '0';
                        Data_Valid <= '1';
                    end if;
 
                when DATA =>            -- Process input data, count the transmitted bytes, send data to output and CRC-24
                    Byte_Counter <= Byte_Counter + 8;
                    CRC24_TX <= Data_temp;
                    Data_temp <= "001"&Data_in;
                    Data_valid <= Data_valid_temp;
                    Data_valid_temp <= Data_in_valid;
                    Data_Control <= '0';
--                    if Data_in_valid = '0' then
--                        Data_Control <= '1';
--                        Data_temp <= X"8000_0001_0000_0000";
--                    end if;
                    CRC24_RST <= '0';
                    CRC24_EN <= Data_in_valid;  -- <= '1' --Data_in_valid; -- Makes CRC-32 error
                    FIFO_readreq <= '1';
 
                    --added
                    if(FIFO_meta = '0') then
                        Data_valid <= '0';
                    end if;
 
                    if (Byte_Counter >= (BurstMax-8)) then
                        FIFO_readreq <= '0';
                    elsif(TX_EOP = '1' ) then
                        FIFO_readreq <= '0';
                    end if;
 
                    if (CRC24_P1 = '1') then
                        CRC24_RST <= '1';
                        CRC24_P1 <= '0';
                    end if;
 
                    if Word_Control_out = '1' then
                        Data_Control <= '1';
                        Word_Control_out <= '0';
                        CRC24_P1 <= '1';
                    end if;
 
                    if Word_valid_out = '1' then
                        Data_valid_temp <= '1';
                        word_valid_out <= '0';
                    end if;
 
                    if valid_temp = '1' then
                        Data_valid_temp <= '1';
                        valid_temp <= '0';
                    end if;
 
                when WORD =>        -- Reset byte count, send frame to CRC-24, stop reading FIFO to make room for output frame 
                    FIFO_readreq <= '1';
                    Byte_Counter <= 0;
                    CRC24_EN <= '1';
 
                    CRC24_TX <= Data_temp;
                    Data_temp <= "010"&X"C000_0001_0000_0000"; -- Burst no start nor end packet (Idle words)
                    --Data_temp(55 downto 40) <= RX_prog_full;
 
                    Data_valid <= Data_valid_temp;
                    Data_valid_temp <= '1';
                    if (Data_in_valid = '1') then
                        Word_valid_out <= '1';
                    end if;
                    Word_Control_out <= '1';
 
                when EOP_SET =>     -- Transmit last bytes from buffer and add this to byte count
                    Byte_Counter <= Byte_Counter + 8;
 
                    CRC24_TX <= Data_temp;
                    Data_temp <= "001"&Data_in; -- Still read out data and save because FIFO takes a cycle to respond
 
                    Data_valid <= Data_valid_temp;
                    Data_valid_temp <= Data_in_valid;
 
                    HealthLane <= '1';     -- set status of lane to healthy
                    HealthInterface <= '1'; -- set status of interface to healthy
 
                    Data_Control <= '0';
                    CRC24_EN <= '1';
                    CRC24_RST <= '0';
                    if (CRC24_P1 = '1') then
                        CRC24_RST <= '1';
                        CRC24_P1 <= '0';
                    end if;
 
                when EOP_EMPTY =>       -- Count bytes, send frame to CRC-24 and output idle word containing CRC and EOP
                    if (Byte_Counter >= BurstShort) then
                         FIFO_readreq <= '1';
                    end if;
                    Byte_Counter <= Byte_Counter + 8; --
 
                    CRC24_TX <= "010"&X"9000_0001_0000_0000"; -- Burst end packet 1001
                    --CRC24_TX(55 downto 40) <= RX_prog_full;
                    CRC24_TX(59 downto 57) <= TX_ValidBytes_s;  -- '1' & TX_ValidBytes_s; 
                    Data_Valid <= '1';
                    Data_Control <= '1';
 
                When FILL =>            -- Continue sending idle words to fill up the minimum frame length
    --                FIFO_readreq <= '1';
                    Byte_Counter <= Byte_Counter + 8;
                    CRC24_TX <= "010"&X"8000_0001_0000_0000"; -- Idle fill packets 1000
                    --CRC24_TX(55 downto 40) <= RX_prog_full;
                    CRC24_EN <= '0';
                    Data_Valid <= '1';
                    CRC24_RST <= '1';
                    if (Byte_Counter >= BurstShort-8) then
                        FIFO_readreq <= '1';
                    end if;
 
                when EOP_FULL =>        -- Send frame to CRC-24 and output burst word containing CRC and EOP
                    FIFO_readreq <= '1';
                    CRC24_TX <= "010"&X"9000_0001_0000_0000"; -- Burst end packet -> 1101 if more data follows or 1001 if no data follows
                    CRC24_TX(60 downto 57) <= '1' & TX_ValidBytes_s;
                    --CRC24_TX(55 downto 40) <= RX_prog_full;
                    Data_Valid <= '1';
                    Data_Control <= '1';
 
                end case;
            else
                CRC24_RST <= CRC24_RST;
                if data_in_valid = '1' then
                    valid_temp <= '1';
                end if;
            end if;
            end if;
        end process output;
 
end architecture framing;

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[/] [core1990_interlaken/] [trunk/] [gateware/] [sources/] [interlaken/] [transmitter/] [framing_burst.vhd] - Blame information for rev 11

Line No.	Rev	Author	Line
1	11	N.Boukadid	`library ieee;`
2			`use ieee.std_logic_1164.all;`
3
4			`entity Burst_Framer is`
5			`generic (`
6			`BurstMax : positive; -- Configurable value of BurstMax`
7			`BurstShort : positive -- Configurable value of BurstShort`
8			`);`
9			`port (`
10			`clk : in std_logic; -- System clock`
11			`reset : in std_logic; -- Reset, use for initialization`
12
13			`TX_Enable : in std_logic; -- Enable the TX`
14			`TX_SOP : in std_logic; -- Start of Packet`
15			`TX_ValidBytes : in std_logic_vector(2 downto 0); -- Valid bytes packet contains`
16			`TX_EOP : in std_logic; -- End of Packet`
17			`TX_Channel : in std_logic_vector(7 downto 0); -- Select transmit channel (yet unutilized)`
18
19			`Data_in : in std_logic_vector(63 downto 0); -- Input data`
20			`Data_in_valid : in std_logic ; -- 1 means that the fifo data was successfully read`
21			`Data_out : out std_logic_vector(66 downto 0); -- To scrambling/framing`
22			`Data_valid_out : out std_logic; -- Indicate data transmitted is valid`
23			`--Data_control_out : out std_logic; -- Control word indication`
24
25			`HealthLane : out std_logic; -- Lane status bit transmitted for diagnostic word`
26			`HealthInterface : out std_logic; -- Interface status bit transmitted for diagnostic word`
27
28			`TX_FlowControl : in std_logic_vector(15 downto 0); -- Flow control data (yet unutilized)`
29			`RX_prog_full : in std_logic_vector(15 downto 0);`
30
31			`FIFO_Empty : in std_logic;`
32
33			`FIFO_meta : in std_logic; -- Request from the MetaFraming to read data from the FIFO`
34			`FIFO_data : in std_logic_vector(4 downto 0); -- Determines how many bytes have to be transmitted (yet unutilized)`
35			`FIFO_read : out std_logic; -- Request data from the FIFO`
36			`Gearboxready : in std_logic`
37			`);`
38			`end Burst_Framer;`
39
40			`architecture framing of Burst_Framer is`
41			`type state_type is (IDLE, DATA, WORD, FILL, EOP_SET, EOP_FULL, EOP_EMPTY);`
42			`signal pres_state, next_state : state_type;`
43
44			`signal Data_Temp : std_logic_vector(66 downto 0) := (others => '0');`
45			`signal Byte_Counter : integer range 0 to 80;`
46			`signal Word_Control_out : std_logic;`
47			`signal Data_Control : std_logic;`
48			`signal Data_Valid : std_logic := '0';`
49			`signal FIFO_readreq : std_logic;`
50			`signal Word_valid_out : std_logic;`
51			`signal HDR_P1, HDR_P2 : std_logic_vector(2 downto 0);`
52			`signal Valid_P1, Valid_P2 : std_logic`
53			`;`
54
55			`signal Data_P1, Data_P2 : std_logic_vector(63 downto 0); -- Pipelined data`
56			`--signal ControlValid_P1, ControlValid_P2 : std_logic_vector(1 downto 0); -- Pipelined control/valid indicator`
57			`signal Data_valid_temp : std_logic;`
58			`signal valid_temp : std_logic := '0';`
59
60			`signal CRC24_TX : std_logic_vector(66 downto 0) := (others => '0'); -- Data transmitted to CRC-24`
61			`signal CRC24_Out : std_logic_vector(23 downto 0); -- Calculated CRC-24 which returns`
62			`signal CRC24_En : std_logic; --l -- Indicate the CRC-24 the data is valid`
63			`signal CRC24_RST : std_logic; -- CRC24 reset`
64			`signal CRC24_P1 : std_logic; -- CRC24 reset pipelining`
65			`--signal CRC24_RST_P1 : std_logic; -- CRC24 reset pipelining`
66			`signal CRC24_Stored : std_logic_vector(31 downto 0);`
67			`signal CRC24_Ready : std_logic;`
68			`signal CRC_P1, CRC_P2 : std_logic;`
69
70			`signal Gearboxready_P1 : std_logic;`
71			`signal CalcCrc : std_logic; -- CRC24_EN and Gearboxready`
72			`signal TX_ValidBytes_s : std_logic_vector(2 downto 0);`
73
74			`-- Constants`
75			`-- constant SOP : std_logic_vector(2 downto 0) := "100"; -- Start Of Packet`
76			`-- constant EOP : std_logic_vector(2 downto 0) := "001"; -- End Of Pack`
77
78
79
80			`begin`
81
82			`CRC_24_Encoding : entity work.CRC_24 -- Define the connections of the CRC-24 component to the Burst component and generics`
83			`--generic map`
84			`--(`
85			`-- Nbits => 64,`
86			`-- CRC_Width => 24,`
87			`-- G_Poly => X"32_8B63", --Test with CRC-32 : 1EDC_6F41 (Interlaken-24 : X"32_8B63") previous: 04C11DB7`
88			`-- G_InitVal => X"FF_FFFF"`
89			`--)`
90			`port map`
91			`(`
92			`Clk => Clk,`
93			`DIn => CRC24_TX(63 downto 0),`
94			`CRC => CRC24_Out,`
95			`Calc => CalcCrc,`
96			`Reset => CRC24_RST`
97			`);`
98
99			`CalcCrc <= Gearboxready and FIFO_meta;`
100
101
102			`pipeline : process (clk, reset)`
103			`variable CRC24_Out_v: std_logic_vector(23 downto 0);`
104			`variable Data_valid_check : std_logic;`
105			`begin`
106			`if (reset = '1') then`
107			`Data_P1 <= (others => '0');`
108			`Data_P2 <= (others => '0');`
109			`Data_out <= (others => '0');`
110			`CRC24_Stored <= (others => '0');`
111			`--ControlValid_P1 <= "00";`
112			`--ControlValid_P2 <= "00";`
113			`--Data_Control_Out <= '0';`
114			`Data_Valid_Out <= '0';`
115			`CRC24_Ready <= '0';`
116			`--CRC24_RST_P1 <= '0';`
117			`elsif (rising_edge(clk)) then`
118			`-- if (CRC24_Rst <= '1') then`
119			`-- CRC24_PP1 <= '1';`
120			`-- else`
121			`-- CRC24_PP1 <= CRC24_PP1;`
122			`-- end if;`
123			`--CRC24_PP1 <= CRC24_PP1;`
124			`--Data_control_out <= '0';`
125
126			`-- if(CRC24_Rst_P1 = '1' and (Data_P2(62 downto 60) = "100" or Data_P2(61 downto 60) = "01")) then`
127			`-- CRC24_Out_v := CRC24_Out;`
128			`-- end if;`
129
130			`Data_Valid_Out <= '0';`
131			`CRC_P1 <= '0';`
132
133			`Gearboxready_P1 <= Gearboxready;`
134			`--CRC24_Rst_P1 <= CRC24_Rst;`
135
136			`if(CRC24_TX(62 downto 60) = "100" or CRC24_TX(61 downto 60) = "01") then`
137			`CRC_P1 <= '1';`
138			`end if;`
139			`CRC_P2 <= CRC_P1;`
140
141			`if (CRC_P2 = '1') then`
142			`CRC24_Out_v := CRC24_Out;`
143			`end if;`
144
145			`if(Gearboxready = '1' and FIFO_meta = '1') then`
146			`Data_P1 <= CRC24_TX(63 downto 0);`
147			`Data_P2 <= Data_P1;`
148			`Data_out(63 downto 0) <= Data_P2;`
149
150			`HDR_P1 <= CRC24_TX(66 downto 64);`
151			`HDR_P2 <= HDR_P1;`
152			`Data_Out(66 downto 64) <= HDR_P2;`
153
154			`Valid_P1 <= Data_Valid;`
155			`Valid_P2 <= Valid_P1;`
156			`Data_Valid_Out <= Valid_P2;`
157			`Data_valid_check := Valid_P2;`
158
159			`--if(HDR_P2 = "010"and(Data_P2(62 downto 60) = "110" or Data_P2(61 downto 60) = "01")) then --Control word BurstMax or EOP only word`
160			`if(HDR_P2 = "010"and(Data_P2(61 downto 60) = "01")) then --Control word BurstMax or EOP only word`
161			`Data_out(23 downto 0) <= CRC24_Out_v; -- Include CRC in last packet of burst`
162			`end if;`
163
164			`if(Valid_P2 = '0') then`
165			`Data_Out <= "010"&X"8000_0001_0000_0000"; -- Idle control word`
166			`end if;`
167
168			`--CRC24_PP1 <= CRC24_Rst;`
169			`end if;`
170
171			`if(Data_valid_check = '0') then`
172			`Data_Out <= "010"&X"8000_0001_0000_0000"; -- Idle control word`
173			`end if;`
174
175			`-- CRC24_RST_P1 <= CRC24_Rst;`
176
177			`-- if (CRC24_RST_P1 = '1') then`
178			`-- if(ControlValid_P2(1) = '1' and Gearboxready = '1' and FIFO_meta = '1' and CRC24_Ready = '0') then`
179			`-- Data_out(31 downto 0) <= CRC24_Out; -- Include CRC in last packet of burst`
180			`-- else`
181			`-- if (CRC24_Ready = '0') then`
182			`-- CRC24_Stored <= CRC24_Out;`
183			`-- CRC24_Ready <= '1';`
184			`-- end if;`
185			`-- end if;`
186			`-- end if;`
187
188			`-- if (CRC24_Ready = '1' and ControlValid_P2(1) = '1' and Gearboxready = '1' and FIFO_meta = '1') then`
189			`-- Data_out(31 downto 0) <= CRC24_Stored;`
190			`-- CRC24_Ready <= '0';`
191			`-- end if;`
192
193			`end if;`
194			`end process pipeline;`
195
196			`-- valid : process(FIFO_meta, Gearboxready, data_in_valid)`
197			`-- begin`
198			`-- --if(rising_edge(clk)) then`
199			`-- if(Gearboxready = '0' or FIFO_meta = '0') and data_in_valid = '1' then`
200			`-- valid_temp <= '1';`
201			`-- end if;`
202			`-- -- end if;`
203			`-- end process valid;`
204
205			`fifo_reading : process (FIFO_meta, FIFO_readreq, Gearboxready, FIFO_Empty) is`
206			`begin`
207			`if (FIFO_meta = '1' and FIFO_readreq = '1' and Gearboxready = '1' and FIFO_Empty = '0') then`
208			`FIFO_read <= '1';`
209			`else`
210			`FIFO_read <= '0';`
211			`end if;`
212			`end process fifo_reading;`
213
214			`state_register : process (clk) is -- Determines the next state of the FSM`
215			`begin`
216			`if (rising_edge(clk)) then`
217			`pres_state <= next_state;`
218			`if TX_EOP = '1' then`
219			`TX_ValidBytes_s <= TX_ValidBytes;`
220			`end if;`
221			`end if;`
222			`end process state_register;`
223
224			`state_decoder : process (pres_state, TX_SOP, TX_Enable, TX_EOP, Byte_Counter, FIFO_meta, Gearboxready) is`
225			`begin`
226			`if(Gearboxready = '0' or FIFO_meta = '0') then`
227			`next_state <= pres_state;`
228			`else`
229			`case pres_state is`
230			`when IDLE =>`
231			`if (TX_Enable = '1' and TX_SOP = '1' and TX_EOP = '0') then`
232			`next_state <= DATA;`
233			`elsif (TX_Enable = '1' and TX_SOP = '1' and TX_EOP = '1') then`
234			`next_state <= EOP_SET;`
235			`else`
236			`next_state <= IDLE;`
237			`end if;`
238			`when DATA =>`
239			`if(TX_EOP = '1' ) then`
240			`next_state <= EOP_SET;`
241			`elsif (Byte_Counter >= (BurstMax-8)) then`
242			`next_state <= WORD;`
243			`else`
244			`next_state <= DATA;`
245			`end if;`
246			`when WORD =>`
247			`next_state <= DATA;`
248			`when EOP_SET =>`
249			`if (Byte_Counter >= BurstShort) then`
250			`next_state <= EOP_FULL;`
251			`else`
252			`next_state <= EOP_EMPTY;`
253			`end if;`
254			`when EOP_EMPTY =>`
255			`if (Byte_Counter >= BurstShort) then`
256			`next_state <= IDLE;`
257			`else`
258			`next_state <= FILL;`
259			`end if;`
260			`when FILL =>`
261			`if (Byte_Counter >= BurstShort-8) then`
262			`next_state <= IDLE;`
263			`else`
264			`next_state <= FILL;`
265			`end if;`
266			`when EOP_FULL =>`
267			`next_state <= IDLE;`
268			`when others =>`
269			`next_state <= IDLE;`
270			`end case;`
271			`end if;`
272			`end process state_decoder;`
273
274			`output : process (pres_state, clk) is`
275			`begin`
276			`if rising_edge(clk) then`
277			`CRC24_RST <= '0';`
278			`-- X"Type/SOP/EOP(2)FlowC(2)_FlowC(2)Channel(2)_Mutiple(2)CRC24(2)_CRC24(2)CRC24(2)" Structure of packet`
279			`if(Gearboxready = '1' and FIFO_meta = '1' ) then`
280			`case pres_state is`
281			`when IDLE => -- Wait for SOP, start reading FIFO and save last cycle data`
282			`CRC24_EN <= '0'; -- Reset CRC calculations`
283			`CRC24_RST <= '1';`
284			`Data_Valid <= '0';`
285			`Word_Control_out <= '0';`
286			`FIFO_readreq <= '1';`
287			`Byte_Counter <= 8;`
288			`CRC24_P1 <= '0';`
289			`Data_Control <= '0';`
290			`valid_temp <= '0';`
291
292			`Data_temp <= "001"&Data_in;`
293			`Data_valid_temp <= Data_in_valid;`
294
295			`if (TX_SOP = '1' and TX_Enable = '1') then -- Indicates the start of data flow`
296			`CRC24_TX <= "010"&X"E000_0001_0000_0000"; -- Start packet E000_0001_0000_0000`
297			`--CRC24_TX(55 downto 40) <= RX_prog_full;`
298			`Data_Valid <= '1';`
299			`Data_valid_temp <= '1'; --Start of a new packet is always valid`
300			`-- elsif (TX_flowcontrol(0) = '0') then -- TODO Flowcontrol is not used? why as condition?`
301			`-- CRC24_TX <= "010"&X"C000_0001_0000_0000"; -- C000_0001_0000_0000`
302			`-- CRC24_TX(55 downto 40) <= RX_prog_full;`
303
304			`else`
305			`CRC24_TX <= "001"&X"0000_0000_0000_0000"; -- data word placeholder`
306			`end if;`
307
308			`if(TX_EOP = '1' and TX_SOP = '1') then`
309			`FIFO_readreq <= '0';`
310			`Data_Valid <= '1';`
311			`end if;`
312
313			`when DATA => -- Process input data, count the transmitted bytes, send data to output and CRC-24`
314			`Byte_Counter <= Byte_Counter + 8;`
315			`CRC24_TX <= Data_temp;`
316			`Data_temp <= "001"&Data_in;`
317			`Data_valid <= Data_valid_temp;`
318			`Data_valid_temp <= Data_in_valid;`
319			`Data_Control <= '0';`
320			`-- if Data_in_valid = '0' then`
321			`-- Data_Control <= '1';`
322			`-- Data_temp <= X"8000_0001_0000_0000";`
323			`-- end if;`
324			`CRC24_RST <= '0';`
325			`CRC24_EN <= Data_in_valid; -- <= '1' --Data_in_valid; -- Makes CRC-32 error`
326			`FIFO_readreq <= '1';`
327
328			`--added`
329			`if(FIFO_meta = '0') then`
330			`Data_valid <= '0';`
331			`end if;`
332
333			`if (Byte_Counter >= (BurstMax-8)) then`
334			`FIFO_readreq <= '0';`
335			`elsif(TX_EOP = '1' ) then`
336			`FIFO_readreq <= '0';`
337			`end if;`
338
339			`if (CRC24_P1 = '1') then`
340			`CRC24_RST <= '1';`
341			`CRC24_P1 <= '0';`
342			`end if;`
343
344			`if Word_Control_out = '1' then`
345			`Data_Control <= '1';`
346			`Word_Control_out <= '0';`
347			`CRC24_P1 <= '1';`
348			`end if;`
349
350			`if Word_valid_out = '1' then`
351			`Data_valid_temp <= '1';`
352			`word_valid_out <= '0';`
353			`end if;`
354
355			`if valid_temp = '1' then`
356			`Data_valid_temp <= '1';`
357			`valid_temp <= '0';`
358			`end if;`
359
360			`when WORD => -- Reset byte count, send frame to CRC-24, stop reading FIFO to make room for output frame`
361			`FIFO_readreq <= '1';`
362			`Byte_Counter <= 0;`
363			`CRC24_EN <= '1';`
364
365			`CRC24_TX <= Data_temp;`
366			`Data_temp <= "010"&X"C000_0001_0000_0000"; -- Burst no start nor end packet (Idle words)`
367			`--Data_temp(55 downto 40) <= RX_prog_full;`
368
369			`Data_valid <= Data_valid_temp;`
370			`Data_valid_temp <= '1';`
371			`if (Data_in_valid = '1') then`
372			`Word_valid_out <= '1';`
373			`end if;`
374			`Word_Control_out <= '1';`
375
376			`when EOP_SET => -- Transmit last bytes from buffer and add this to byte count`
377			`Byte_Counter <= Byte_Counter + 8;`
378
379			`CRC24_TX <= Data_temp;`
380			`Data_temp <= "001"&Data_in; -- Still read out data and save because FIFO takes a cycle to respond`
381
382			`Data_valid <= Data_valid_temp;`
383			`Data_valid_temp <= Data_in_valid;`
384
385			`HealthLane <= '1'; -- set status of lane to healthy`
386			`HealthInterface <= '1'; -- set status of interface to healthy`
387
388			`Data_Control <= '0';`
389			`CRC24_EN <= '1';`
390			`CRC24_RST <= '0';`
391			`if (CRC24_P1 = '1') then`
392			`CRC24_RST <= '1';`
393			`CRC24_P1 <= '0';`
394			`end if;`
395
396			`when EOP_EMPTY => -- Count bytes, send frame to CRC-24 and output idle word containing CRC and EOP`
397			`if (Byte_Counter >= BurstShort) then`
398			`FIFO_readreq <= '1';`
399			`end if;`
400			`Byte_Counter <= Byte_Counter + 8; --`
401
402			`CRC24_TX <= "010"&X"9000_0001_0000_0000"; -- Burst end packet 1001`
403			`--CRC24_TX(55 downto 40) <= RX_prog_full;`
404			`CRC24_TX(59 downto 57) <= TX_ValidBytes_s; -- '1' & TX_ValidBytes_s;`
405			`Data_Valid <= '1';`
406			`Data_Control <= '1';`
407
408			`When FILL => -- Continue sending idle words to fill up the minimum frame length`
409			`-- FIFO_readreq <= '1';`
410			`Byte_Counter <= Byte_Counter + 8;`
411			`CRC24_TX <= "010"&X"8000_0001_0000_0000"; -- Idle fill packets 1000`
412			`--CRC24_TX(55 downto 40) <= RX_prog_full;`
413			`CRC24_EN <= '0';`
414			`Data_Valid <= '1';`
415			`CRC24_RST <= '1';`
416			`if (Byte_Counter >= BurstShort-8) then`
417			`FIFO_readreq <= '1';`
418			`end if;`
419
420			`when EOP_FULL => -- Send frame to CRC-24 and output burst word containing CRC and EOP`
421			`FIFO_readreq <= '1';`
422			`CRC24_TX <= "010"&X"9000_0001_0000_0000"; -- Burst end packet -> 1101 if more data follows or 1001 if no data follows`
423			`CRC24_TX(60 downto 57) <= '1' & TX_ValidBytes_s;`
424			`--CRC24_TX(55 downto 40) <= RX_prog_full;`
425			`Data_Valid <= '1';`
426			`Data_Control <= '1';`
427
428			`end case;`
429			`else`
430			`CRC24_RST <= CRC24_RST;`
431			`if data_in_valid = '1' then`
432			`valid_temp <= '1';`
433			`end if;`
434			`end if;`
435			`end if;`
436			`end process output;`
437
438			`end architecture framing;`