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[/] [core1990_interlaken/] [trunk/] [gateware/] [sources/] [interlaken/] [transmitter/] [scrambler.vhd] - Blame information for rev 11

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1 11 N.Boukadid 
library ieee;
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use ieee.std_logic_1164.all;
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entity Scrambler is
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        port (
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                Clk                             : in std_logic;                               -- System clock
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                Scram_Rst               : in std_logic;                               -- Scrambler reset, use for initialization
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                Data_In                 : in std_logic_vector (66 downto 0);  -- Data input
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                Data_Out                : out std_logic_vector (66 downto 0); -- Data output
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                Lane_Number             : in std_logic_vector (3 downto 0);   -- Each lane number starts with different scrambler word
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                Scrambler_En    : in std_logic;                                           -- Input valid
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                --Data_Control_In : in std_logic;                       -- Indicates a control word
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                --Data_Control_Out: out std_logic;                      -- Output control word indication
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                Data_Valid_In   : in std_logic;                       -- Input valid
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        Data_Valid_Out  : out std_logic;                                  -- Output valid
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        Gearboxready    : in std_logic
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        );
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end Scrambler;
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architecture Scrambling of Scrambler is
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        signal Poly : std_logic_vector (57 downto 0);
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        signal Shiftreg : std_logic_vector (63 downto 0);
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            -- Constants
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    constant SYNCHRONIZATION : std_logic_vector(63 downto 0) := X"78f6_78f6_78f6_78f6";  -- synchronization framing layer control word
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    constant SCRAM_STATE_INIT_VALUE : std_logic_vector(63 downto 0) := X"2800_0000_0000_0000"; -- Starting value of scrambler
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    constant META_TYPE_SYNCHRONIZATION: std_logic_vector(4 downto 0) := "11110";
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    constant META_TYPE_SCRAM_STATE: std_logic_vector(4 downto 0) := "01010";
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begin
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        shiftreg(63) <= Poly(57) xor Poly(38);
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    shiftreg(62) <= Poly(56) xor Poly(37);
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    shiftreg(61) <= Poly(55) xor Poly(36);
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    shiftreg(60) <= Poly(54) xor Poly(35);
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    shiftreg(59) <= Poly(53) xor Poly(34);
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    shiftreg(58) <= Poly(52) xor Poly(33);
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    shiftreg(57) <= Poly(51) xor Poly(32);
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    shiftreg(56) <= Poly(50) xor Poly(31);
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    shiftreg(55) <= Poly(49) xor Poly(30);
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    shiftreg(54) <= Poly(48) xor Poly(29);
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    shiftreg(53) <= Poly(47) xor Poly(28);
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    shiftreg(52) <= Poly(46) xor Poly(27);
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    shiftreg(51) <= Poly(45) xor Poly(26);
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    shiftreg(50) <= Poly(44) xor Poly(25);
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    shiftreg(49) <= Poly(43) xor Poly(24);
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    shiftreg(48) <= Poly(42) xor Poly(23);
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    shiftreg(47) <= Poly(41) xor Poly(22);
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    shiftreg(46) <= Poly(40) xor Poly(21);
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    shiftreg(45) <= Poly(39) xor Poly(20);
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    shiftreg(44) <= Poly(38) xor Poly(19);
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    shiftreg(43) <= Poly(37) xor Poly(18);
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    shiftreg(42) <= Poly(36) xor Poly(17);
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    shiftreg(41) <= Poly(35) xor Poly(16);
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    shiftreg(40) <= Poly(34) xor Poly(15);
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    shiftreg(39) <= Poly(33) xor Poly(14);
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    shiftreg(38) <= Poly(32) xor Poly(13);
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    shiftreg(37) <= Poly(31) xor Poly(12);
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    shiftreg(36) <= Poly(30) xor Poly(11);
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    shiftreg(35) <= Poly(29) xor Poly(10);
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    shiftreg(34) <= Poly(28) xor Poly(9);
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    shiftreg(33) <= Poly(27) xor Poly(8);
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    shiftreg(32) <= Poly(26) xor Poly(7);
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    shiftreg(31) <= Poly(25) xor Poly(6);
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    shiftreg(30) <= Poly(24) xor Poly(5);
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    shiftreg(29) <= Poly(23) xor Poly(4);
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    shiftreg(28) <= Poly(22) xor Poly(3);
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    shiftreg(27) <= Poly(21) xor Poly(2);
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    shiftreg(26) <= Poly(20) xor Poly(1);
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    shiftreg(25) <= Poly(19) xor Poly(0);
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    shiftreg(24) <= Poly(57) xor Poly(38) xor Poly(18);
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    shiftreg(23) <= Poly(56) xor Poly(37) xor Poly(17);
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    shiftreg(22) <= Poly(55) xor Poly(36) xor Poly(16);
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    shiftreg(21) <= Poly(54) xor Poly(35) xor Poly(15);
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    shiftreg(20) <= Poly(53) xor Poly(34) xor Poly(14);
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    shiftreg(19) <= Poly(52) xor Poly(33) xor Poly(13);
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    shiftreg(18) <= Poly(51) xor Poly(32) xor Poly(12);
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    shiftreg(17) <= Poly(50) xor Poly(31) xor Poly(11);
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    shiftreg(16) <= Poly(49) xor Poly(30) xor Poly(10);
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    shiftreg(15) <= Poly(48) xor Poly(29) xor Poly(9);
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    shiftreg(14) <= Poly(47) xor Poly(28) xor Poly(8);
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    shiftreg(13) <= Poly(46) xor Poly(27) xor Poly(7);
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    shiftreg(12) <= Poly(45) xor Poly(26) xor Poly(6);
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    shiftreg(11) <= Poly(44) xor Poly(25) xor Poly(5);
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    shiftreg(10) <= Poly(43) xor Poly(24) xor Poly(4);
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    shiftreg(9) <= Poly(42) xor Poly(23) xor Poly(3);
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    shiftreg(8) <= Poly(41) xor Poly(22) xor Poly(2);
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    shiftreg(7) <= Poly(40) xor Poly(21) xor Poly(1);
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    shiftreg(6) <= Poly(39) xor Poly(20) xor Poly(0);
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    shiftreg(5) <= Poly(57) xor Poly(19);
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    shiftreg(4) <= Poly(56) xor Poly(18);
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    shiftreg(3) <= Poly(55) xor Poly(17);
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    shiftreg(2) <= Poly(54) xor Poly(16);
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    shiftreg(1) <= Poly(53) xor Poly(15);
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    shiftreg(0) <= Poly(52) xor Poly(14);
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        Scramble : process (Clk, Scram_Rst, lane_number)
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        begin
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        if(Scram_Rst = '1') then
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            Poly                <= (others => '1');
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            Poly(57 downto 54)  <= Lane_Number(3 downto 0);
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            Data_Out            <= (others => '0');
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            --Data_Control_Out    <= '0';
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            Data_Valid_Out      <= '0';
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                elsif (rising_edge(clk)) then
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            --if (Data_Valid_In = '1' and Gearboxready = '1') then
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            if (Gearboxready = '1') then
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                if (Data_In(65 downto 63) = "100") then                     --Checks if incoming data is control word
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                    if(Data_In(62 downto 58)= META_TYPE_SYNCHRONIZATION) then       -- Sync words are not scrambled
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                        Data_Out <= Data_In;
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                    elsif (Data_In(62 downto 58) = META_TYPE_SCRAM_STATE) then   -- Scrambler state words are not scrambled
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                        Data_Out(63 downto 0) <= Data_In(63 downto 58) & Poly;
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                    else
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                        Poly <= shiftreg(57 downto 0);              -- All other control words are scrambled
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                        Data_Out(63 downto 0) <= Data_In(63 downto 0) xor (Poly(57 downto 0) & Shiftreg(63 downto 58));
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                    end if;
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                else
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                    Poly <= shiftreg(57 downto 0);                  -- All data words are scrambled
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                    Data_Out(63 downto 0) <= Data_In(63 downto 0) xor (Poly(57 downto 0) & Shiftreg(63 downto 58));  -- correct
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                end if;
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                Data_Out(65 downto 64) <= Data_In(65 downto 64);  -- Data word header
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                Data_Valid_Out <= Data_Valid_In;
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            end if;
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        end if;
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        end process;
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end architecture Scrambling;

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