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[/] [core1990_interlaken/] [trunk/] [gateware/] [sources/] [interlaken_wrapper_vc707.vhd] - Blame information for rev 11

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1 11 N.Boukadid
library ieee;
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use ieee.std_logic_1164.all;
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library unisim;
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use unisim.vcomponents.all;
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entity Interface_Test is
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    port(
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                System_Clock_In_P : in std_logic;
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                System_Clock_In_N : in std_logic;
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                GTREFCLK_IN_P : in std_logic;
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                GTREFCLK_IN_N : in std_logic;
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                USER_CLK_IN_P : in std_logic;
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                USER_CLK_IN_N : in std_logic;
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                USER_SMA_CLK_OUT_P : out std_logic;
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                USER_SMA_CLK_OUT_N : out std_logic;
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                TX_Out_P     : out std_logic;
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                TX_Out_N     : out std_logic;
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                RX_In_P      : in std_logic;
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                RX_In_N      : in std_logic;
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                Lock_Out  : out std_logic;
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                Valid_out : out std_logic
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    );
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end entity Interface_test;
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architecture Test of Interface_Test is
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    signal TX_Data      : std_logic_vector(63 downto 0);            -- Data transmitted
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    signal RX_Data  : std_logic_vector(63 downto 0);            -- Data received
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    signal TX_SOP          : std_logic;
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    signal TX_EOP          : std_logic;
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    signal TX_EOP_Valid    : std_logic_vector(2 downto 0);
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    signal TX_FlowControl  : std_logic_vector(15 downto 0);
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    signal TX_Channel      : std_logic_vector(7 downto 0);
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    signal RX_SOP               : std_logic;                         -- Start of Packet
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    signal RX_EOP               : std_logic;                         -- End of Packet
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    signal RX_EOP_Valid         : std_logic_vector(2 downto 0);      -- Valid bytes packet contains
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    signal RX_FlowControl       : std_logic_vector(15 downto 0);     -- Flow control data (yet unutilized)
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    signal RX_Channel           : std_logic_vector(7 downto 0);      -- Select transmit channel (yet unutilized)
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    signal RX_Valid_Out     : std_logic;
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    signal TX_FIFO_Full      : std_logic;
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    signal TX_FIFO_progfull  : std_logic;
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    signal TX_FIFO_Write     : std_logic;
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    signal RX_FIFO_Read      : std_logic;
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    signal RX_FIFO_Full      : std_logic;
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    signal Decoder_lock      : std_logic;
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    signal Descrambler_lock  : std_logic;
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    signal CRC24_Error       : std_logic;
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    signal CRC32_Error       : std_logic;
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    signal pipeline_length   : std_logic_vector(6 downto 0);
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    signal TX_Info_Pipelined : std_logic_vector(4 downto 0);
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    signal TX_Data_Pipelined : std_logic_vector(63 downto 0);
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    signal RX_Info           : std_logic_vector(4 downto 0);
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    signal System_Clock      : std_logic;
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        signal valid_probe, RX_Valid : std_logic_vector(0 downto 0);
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        signal packet_length         : std_logic_vector(6 downto 0);
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        signal RX_in                 : std_logic_vector(63 downto 0);
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    signal TX_out                : std_logic_vector(63 downto 0);
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    signal Data_Descrambler      : std_logic_vector(66 downto 0);
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    signal Data_Decoder          : std_logic_vector(66 downto 0);
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    signal probe5_data           : std_logic_vector(2 downto 0);
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        COMPONENT ILA_Data
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        PORT (
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                clk : IN STD_LOGIC;
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                probe0 : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
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                probe1 : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
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                probe2 : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
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                probe3 : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
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        probe4 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
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        probe5 : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
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        probe6 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
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        probe7 : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
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        probe8 : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
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        probe9 : IN STD_LOGIC_VECTOR(66 DOWNTO 0);
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        probe10 : IN STD_LOGIC_VECTOR(66 DOWNTO 0)
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        );
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        END COMPONENT;
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    COMPONENT vio_0
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    PORT (
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        clk : IN STD_LOGIC;
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        probe_out0 : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
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        probe_out1 : OUT STD_LOGIC_VECTOR(6 DOWNTO 0)
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    );
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    END COMPONENT;
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    signal USER_CLK, USER_SMA_CLK: std_logic;
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begin
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    -------Reference clock routing
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    user_clk_ibuf : IBUFDS port map(
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        I => USER_CLK_IN_P,
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        IB => USER_CLK_IN_N,
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        O => USER_CLK
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    );
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    USER_SMA_CLK <= USER_CLK;
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    user_sma_clk_obuf: OBUFDS port map(
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        I => USER_SMA_CLK,
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        O => USER_SMA_CLK_OUT_P,
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        OB => USER_SMA_CLK_OUT_N
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    );
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        ------- The Interlaken Interface -------
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    interface : entity work.interlaken_interface
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    generic map(
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         BurstMax     => 256, --(Bytes)
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         BurstShort   => 64, --(Bytes)
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         PacketLength => 2028 --(Packets)
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    )
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    port map (
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        System_Clock_In_P => System_Clock_In_P,
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        System_Clock_In_N => System_Clock_In_N,
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        GTREFCLK_IN_P => GTREFCLK_IN_P,
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        GTREFCLK_IN_N => GTREFCLK_IN_N,
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        System_Clock_Gen => System_Clock,
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        TX_Data => TX_Data,
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        RX_Data => RX_Data,
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        RX_In_N => RX_In_N,
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        RX_In_P => RX_In_P,
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        TX_Out_N => TX_Out_N,
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        TX_Out_P => TX_Out_P,
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        TX_FIFO_Write => TX_FIFO_Write,
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        TX_SOP => TX_SOP,
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        TX_EOP => TX_EOP,
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        TX_EOP_Valid => TX_EOP_Valid,
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        TX_FlowControl => TX_FlowControl,
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        TX_Channel => TX_Channel,
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        RX_FIFO_Read => RX_FIFO_Read,
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        RX_SOP => RX_SOP,
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        RX_EOP => RX_EOP,
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        RX_EOP_Valid => RX_EOP_Valid,
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        RX_FlowControl => RX_FlowControl,
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        RX_Channel => RX_Channel,
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        TX_FIFO_progfull => TX_FIFO_progfull,
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        RX_Valid_Out => RX_Valid_Out,
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        TX_FIFO_Full => TX_FIFO_Full,
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        RX_FIFO_Full => RX_FIFO_Full,
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        RX_in => RX_in,
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        TX_out => TX_out,
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        Data_Descrambler => Data_Descrambler,
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        Data_Decoder => Data_Decoder,
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        Decoder_lock => Decoder_lock,
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        Descrambler_lock => Descrambler_lock,
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        CRC24_Error => CRC24_Error,
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        CRC32_Error => CRC32_Error
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    );
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    ---- Generates input data and interface signals ----
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    generate_data : entity work.data_generator
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    port map (
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                clk => System_Clock,
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            Packet_length => packet_length,
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            --link_up => Link_up,
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            TX_FIFO_Full => TX_FIFO_progfull,
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            write_enable => TX_FIFO_Write,
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            data_out => TX_Data,
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        sop      => TX_SOP,
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        eop              => TX_EOP,
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        eop_valid=> TX_EOP_Valid,
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        channel  => TX_Channel
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    );
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    ---- Pipelines input data for alignment with output data ----
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    pipeline_data : entity work.pipe
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    generic map (
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                Nmax => 128
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        )
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        port map (
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            N => pipeline_length,
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        clk => System_Clock,
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        pipe_in(68 downto 66) => TX_EOP_Valid,
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        pipe_in(65) => TX_EOP,
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        pipe_in(64) => TX_SOP,
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            pipe_in(63 downto 0) => TX_Data,
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            pipe_out(68 downto 64) => TX_Info_Pipelined,
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            pipe_out(63 downto 0) => TX_Data_Pipelined
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        );
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        RX_Info <= RX_EOP_valid & RX_EOP & RX_SOP;
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        -------- Integrated Logic Analyzer --------
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        probe_data : ILA_Data
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        PORT MAP (
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                clk => System_Clock,
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                probe0 => TX_Data_Pipelined,
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                probe1 => TX_Info_Pipelined,
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                probe2 => RX_Data,
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                probe3 => RX_Info,
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                probe4 => valid_probe,
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                probe5 => probe5_data,
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                probe6 => RX_Valid,
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                probe7 => RX_in,
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                probe8 => TX_out,
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                probe9 => Data_Descrambler,
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                probe10 => Data_Decoder
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        );
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        probe5_data <= TX_FIFO_progfull & Decoder_Lock & Descrambler_Lock;
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        RX_Valid(0) <= RX_Valid_Out;
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        -------- Validates the data integrity ---------
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        valid : process (TX_data_pipelined, RX_data, TX_info_pipelined, RX_info)
226
        begin
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           if(TX_Data_Pipelined = RX_Data and TX_info_pipelined = RX_info) then
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               valid_out <= '1';
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               valid_probe <= "1";
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       else
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           valid_out <= '0';
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           valid_probe <= "0";
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       end if;
234
    end process;
235
    RX_FIFO_Read <= not TX_FIFO_progfull;
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    ------------- Virtual input/output -------------
238
    VIO : vio_0
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    PORT MAP (
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        clk => System_Clock,
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        probe_out0 => packet_length,
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        probe_out1 => pipeline_length
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    );
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    --------------- Lock detection ---------------
246
    lock : process (Descrambler_Lock)
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    begin
248
        if (Descrambler_Lock = '1') then
249
            Lock_Out <= '1';
250
        else
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            Lock_Out <= '0';
252
        end if;
253
    end process;
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end architecture Test;

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