Subversion Repositories core1990_interlaken

library ieee, UNISIM, work;

use ieee.numeric_std.all;

use UNISIM.VCOMPONENTS.all;

use ieee.std_logic_unsigned.all;

use ieee.std_logic_1164.all;

use work.interlaken_pkg.all;

entity interlaken_wrapper is

  port (

    SYSCLK_P       : in     std_logic;--200 MHz clock at H19/G18

    SYSCLK_N       : in     std_logic;

    GTREFCLK_IN_P  : in     std_logic; -- Transceiver SFP clock

    GTREFCLK_IN_N  : in     std_logic;

    REC_CLOCK_C_P  : out    std_logic; -- Input clock signal for SI5324 (Clock cleaner)

    REC_CLOCK_C_N  : out    std_logic;

    USER_CLK_IN_P  : in     std_logic; -- 156.25 MHZ cristal output 

    USER_CLK_IN_N  : in     std_logic;

    TX_Out_P       : out    std_logic;

    TX_Out_N       : out    std_logic;

    RX_In_P        : in     std_logic;

    RX_In_N        : in     std_logic;

    SFP_RX_LOS     : in     std_logic_vector(3 downto 0)

  );

end entity interlaken_wrapper;

architecture rtl of interlaken_wrapper is

  signal reset                    : std_logic;

  ---- Interlaken instance signals

  signal RX_FlowControl_s     : std_logic_vector(15 downto 0);

  signal RX_Channel_s         : std_logic_vector(7 downto 0) := "00000001";

  signal TX_Channel_s         : std_logic_vector(7 downto 0);

  signal TX_FIFO_progfull_s   : std_logic;

  signal TX_Data_s            : std_logic_vector(63 downto 0);

  signal TX_FIFO_Full_s       : std_logic;

  signal TX_FIFO_Write_s      : std_logic;

  signal TX_SOP_s             : std_logic;

  signal TX_SOP_s_p1          : std_logic;

  signal TX_EOP_s             : std_logic;

  signal TX_EOP_Valid_s       : std_logic_vector(2 downto 0);

  --signal  TX_FIFO_Valid        : std_logic;

  signal RX_Data_s            : std_logic_vector(63 downto 0);

  signal RX_FIFO_Read_s       : std_logic;

  signal RX_FIFO_Empty_s      : std_logic;

  signal RX_FIFO_FULL_s       : std_logic;

  signal RX_SOP_s             : std_logic;

  signal RX_EOP_s             : std_logic;

  signal RX_EOP_Valid_s       : std_logic_vector(2 downto 0);

  signal RX_FIFO_Valid        : std_logic;

  signal RX_FIFO_Valid_p1     : std_logic;

  signal RX_FIFO_Read_s_p1    : std_logic;

  signal RX_Info              : std_logic_vector(4 downto 0);

  signal CRC24_Error_s        : std_logic := '0';

  signal CRC24_occured        : std_logic := '0';

  signal CRC32_Error_s        : std_logic := '0';

  signal CRC32_occured        : std_logic := '0';

  signal send_sync_word       : std_logic;

  signal send_sync_word_p1    : std_logic;

  signal send_sync_word_p2    : std_logic;

  signal RX_EOP_s_p1          : std_logic;

  signal Decoder_lock_s       : std_logic; --interlaken_monitor_type;

  signal Descrambler_lock_s   : std_logic;

  signal PacketLength         : std_logic_vector(15 downto 0) := X"0010";

  signal clk40                : std_logic;

  signal clk150               : std_logic;

  signal locked               : std_logic;

  signal reset_hard_soft      : std_logic; --hard and soft reset coming from wupper, input to clk_40MHz reset. locked output is used to reset the application.

  signal loopback_in          : std_logic_vector(2 downto 0);

  ---- signals related to test data generation -----------

  signal pipeline_length   : std_logic_vector(6 downto 0);

  signal TX_Info_Pipelined : std_logic_vector(4 downto 0);

  signal TX_Data_Pipelined : std_logic_vector(63 downto 0);

  signal System_Clock      : std_logic;

  signal Lock_Out              : std_logic; -- used to be ext status led

  signal valid_out             : std_logic; -- used to be ext status led

  signal valid_probe, RX_Valid : std_logic_vector(0 downto 0);

  signal packet_length         : std_logic_vector(6 downto 0);

  signal RX_in                 : std_logic_vector(63 downto 0);

  signal TX_out                : std_logic_vector(63 downto 0);

  signal Data_Descrambler      : std_logic_vector(63 downto 0);

  signal Data_Decoder          : std_logic_vector(63 downto 0);

  signal probe5_data           : std_logic_vector(2 downto 0);

     -------------------------- Generate System Clock ---------------------------

  component clk_40MHz

  port (

    --Clock in- and output signals

    clk_in1_p  : in     std_logic;

    clk_in1_n  : in     std_logic;

    clk_out1   : out    std_logic;

    clk_out2   : out    std_logic;

    -- Status and control signals

    locked     : out    std_logic;

    reset      : in     std_logic

  );

  end component;

  component ILA_Data

  port (

    clk : in std_logic;

    probe0 : in std_logic_vector(63 downto 0);

    probe1 : in std_logic_vector(4 downto 0);

    probe2 : in std_logic_vector(63 downto 0);

    probe3 : in std_logic_vector(4 downto 0);

    probe4 : in std_logic_vector(0 downto 0);

    probe5 : in std_logic_vector(2 downto 0);

    probe6 : in std_logic_vector(0 downto 0);

    probe7 : in std_logic_vector(63 downto 0);

    probe8 : in std_logic_vector(63 downto 0);

    probe9 : in std_logic_vector(63 downto 0);

    probe10: in std_logic_vector(63 downto 0)

  );

  end component;

  component vio_0

  port (

      clk : in std_logic;

      probe_out0 : out std_logic_vector(6 downto 0);

      probe_out1 : out std_logic_vector(6 downto 0)

  );

  end component;

begin

  ------------------------ Generating stable clock --------------------------

  -- Block to internally connect the 156.25 MHz clock to the SI5324 

  clock_buffer: block

   signal IB_Buf_ds_out  : std_logic;

   signal Buf_G_out      : std_logic;

  begin

    IBUFDS_inst:IBUFDS

    generic map (

      DIFF_TERM => TRUE,

      IBUF_LOW_PWR => FALSE,

      IOSTANDARD => "LVDS")

    port map  (

      O  => IB_Buf_ds_out,

      I  => USER_CLK_IN_P,

      IB => USER_CLK_IN_N

    );

    BUFG_inst : BUFG

    port map (

      O => Buf_G_out,

      I => IB_Buf_ds_out

    );

    OBUFDS_inst: OBUFDS

    generic map (

      IOSTANDARD => "LVDS",

      SLEW => "SLOW" )

    port map (

      O => REC_CLOCK_C_P,

      OB => REC_CLOCK_C_N,

      I => Buf_G_out

    );

  end block;

  -------------------------- Generating 40/150 clk  --------------------------

  system_clock_proc : clk_40MHz

  port map (

    clk_in1_p => SYSCLK_P, --200 MHz clock at H19/G18

    clk_in1_n => SYSCLK_N,

    clk_out1 => clk40,

    clk_out2 => clk150,

    locked   => locked,

    reset    => '0'

  );

 system_clock <= clk150;

 reset <= not locked;

  ---------------------------- Interlaken core ------------------------------

  il0: entity work.interlaken_interface

    generic map(

      BurstMax     => 256,      -- Configurable value of BurstMax

      BurstShort   => 64,       -- Configurable value of BurstShort

      PacketLength => 2024)     -- Configurable value of PacketLength -- 24 packets * 8  = 192 B

    port map(

      ----40 MHz input, from clock generator------------

      clk40  => clk40,

      clk150 => clk150,

      reset  => reset,

      ----125 MHz input, to transceiver (SGMII clock)--

      GTREFCLK_IN_P => GTREFCLK_IN_P,

      GTREFCLK_IN_N => GTREFCLK_IN_N,

      ----Data signals---------------------------------

      TX_Data     => tx_data_s, --fromHostFifo_dout,     

      RX_Data     => rx_data_s, -- toHostFifo_din,       

      ----Transceiver related transmission-------------

      TX_Out_P  => TX_Out_P,

      TX_Out_N  => TX_Out_N,

      RX_In_P   => RX_In_P,

      RX_In_N   => RX_In_N,

      ----Transmitter input/ready signals--------------

      TX_SOP            => TX_SOP_s,

      TX_EOP            => TX_EOP_s,

      TX_EOP_Valid      => TX_EOP_Valid_s,

      TX_FlowControl    => RX_FlowControl_s,

      TX_Channel        => TX_Channel_s,

      ----Receiver output signals-------------    

      RX_SOP            => RX_SOP_s,

      RX_EOP            => RX_EOP_s,

      RX_EOP_Valid      => RX_EOP_Valid_s,

      RX_FlowControl    => RX_FlowControl_s,

      RX_Channel        => RX_Channel_s,

      RX_FIFO_Valid     => RX_FIFO_Valid,

      RX_FIFO_Read      => RX_FIFO_Read_s,

      ----Transmitter status signals----------   

      TX_FIFO_Full      => TX_FIFO_Full_s,

      TX_FIFO_Write     => TX_FIFO_Write_s,

      TX_FIFO_progfull  => TX_FIFO_progfull_s,

      ----Receiver status signals-------------

      RX_FIFO_Full      => RX_FIFO_FULL_s,

      RX_FIFO_Empty     => RX_FIFO_Empty_s,

      Decoder_lock      => Decoder_lock_s ,

      Descrambler_lock  => Descrambler_lock_s ,--interlaken_monitor.INTERLAKEN_CONTROL_STATUS.DESCRAMBLER_LOCK(0),              

      CRC24_Error       => CRC24_Error_s,

      CRC32_Error       => CRC32_Error_s,

      loopback_in       => loopback_in

    );

    -------- Register variables --------------------

--    PacketLength <= register_map_control.INTERLAKEN_PACKET_LENGTH;

--    interlaken_monitor.TRANSCEIVER.RX_LOS <= SFP_RX_LOS; --Loss Of Signal register

--    loopback_in <= '0' & register_map_control.TRANSCEIVER.LOOPBACK & '0' ;  -- Assign register loopback value.

--    interlaken_monitor.INTERLAKEN_CONTROL_STATUS.DECODER_LOCK(1)  <= Decoder_lock_s ;

--    interlaken_monitor.INTERLAKEN_CONTROL_STATUS.DESCRAMBLER_LOCK(0) <= Descrambler_lock_s;

    send_sync_word <= RX_EOP_s AND (NOT send_sync_word_p1) and RX_FIFO_valid;

    ---- Generates input data and interface signals ----

    generate_data : entity work.data_generator

    port map (

                clk => System_Clock,

            Packet_length => packet_length,

            --link_up => Link_up,

            TX_FIFO_Full => TX_FIFO_progfull_s,

            write_enable => TX_FIFO_Write_s,

            data_out => TX_Data_s,

        sop      => TX_SOP_s,

        eop              => TX_EOP_s,

        eop_valid=> TX_EOP_Valid_s,

        channel  => TX_Channel_s

    );

    ---- Pipelines input data for alignment with output data ----

    pipeline_data : entity work.pipe

    generic map (

                Nmax => 128

        )

        port map (

            N => pipeline_length,

        clk => System_Clock,

        pipe_in(68 downto 66) => TX_EOP_Valid_s,

        pipe_in(65) => TX_EOP_s,

        pipe_in(64) => TX_SOP_s,

            pipe_in(63 downto 0) => TX_Data_s,

            pipe_out(68 downto 64) => TX_Info_Pipelined,

            pipe_out(63 downto 0) => TX_Data_Pipelined

        );

        RX_Info <= RX_EOP_valid_s & RX_EOP_s & RX_SOP_s;

        -------- Integrated Logic Analyzer --------

        probe_data : ila_data

        PORT MAP (

                clk => System_Clock,

                probe0 => TX_Data_Pipelined,

                probe1 => TX_Info_Pipelined,

                probe2 => RX_Data_s,

                probe3 => RX_Info,

                probe4 => valid_probe,

                probe5 => probe5_data,

                probe6 => RX_Valid,

                probe7 => RX_in,

                probe8 => TX_out,

                probe9 => Data_Descrambler,

                probe10 => Data_Decoder

        );

        probe5_data <= TX_FIFO_progfull_s & Decoder_Lock_s & Descrambler_Lock_s;

        RX_Valid(0) <= RX_FIFO_Valid;

        -------- Validates the data integrity ---------

        valid : process (TX_data_pipelined, RX_data_s, TX_info_pipelined, RX_info)

        begin

           if(TX_Data_Pipelined = RX_Data_s and TX_info_pipelined = RX_info) then

               valid_out <= '1';

               valid_probe <= "1";

       else

           valid_out <= '0';

           valid_probe <= "0";

       end if;

    end process;

    RX_FIFO_Read_s <= not TX_FIFO_progfull_s;

    ------------- Virtual input/output -------------

    VIO : vio_0

    PORT MAP (

        clk => System_Clock,

        probe_out0 => packet_length,

        probe_out1 => pipeline_length

    );

    --------------- Lock detection ---------------

    lock : process (Descrambler_Lock_s)

    begin

        if (Descrambler_Lock_s = '1') then

            Lock_Out <= '1';

        else

            Lock_Out <= '0';

        end if;

    end process;

end architecture rtl ; -- of application