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[/] [core1990_interlaken/] [trunk/] [gateware/] [sources/] [ip_cores/] [vc707/] [clk_40MHz.xci] - Blame information for rev 11

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Line No. Rev Author Line
1 11 N.Boukadid
2
3
  xilinx.com
4
  xci
5
  unknown
6
  1.0
7
  
8
    
9
      clk_40MHz
10
      
11
      
12
        MMCM
13
        cddcdone
14
        cddcreq
15
        0000
16
        2800
17
        clkfb_in_n
18
        clkfb_in
19
        clkfb_in_p
20
        SINGLE
21
        clkfb_out_n
22
        clkfb_out
23
        clkfb_out_p
24
        clkfb_stopped
25
        50.0
26
        100.0
27
        130c
28
        2c00
29
        40.000
30
        10c4
31
        0080
32
        150.000
33
        BUFG
34
        50.0
35
        false
36
        40.000
37
        0.000
38
        50.000
39
        40.000
40
        0.000
41
        1
42
        1041
43
        00c0
44
        100.000
45
        BUFG
46
        50.0
47
        false
48
        150.000
49
        0.000
50
        50.000
51
        150.000
52
        0.000
53
        1
54
        1
55
        1041
56
        00c0
57
        100.000
58
        BUFG
59
        50.000
60
        false
61
        100.000
62
        0.000
63
        50.000
64
        100.000
65
        0.000
66
        1
67
        0
68
        1041
69
        00c0
70
        100.000
71
        BUFG
72
        50.000
73
        false
74
        100.000
75
        0.000
76
        50.000
77
        100.000
78
        0.000
79
        1
80
        0
81
        1041
82
        0cc0
83
        100.000
84
        BUFG
85
        50.000
86
        false
87
        100.000
88
        0.000
89
        50.000
90
        100.000
91
        0.000
92
        1
93
        0
94
        1041
95
        28c0
96
        100.000
97
        BUFG
98
        50.000
99
        false
100
        100.000
101
        0.000
102
        50.000
103
        100.000
104
        0.000
105
        1
106
        0
107
        BUFG
108
        50.000
109
        false
110
        100.000
111
        0.000
112
        50.000
113
        100.000
114
        0.000
115
        1
116
        0
117
        VCO
118
        clk_in_sel
119
        clk_out1
120
        clk_out2
121
        clk_out3
122
        clk_out4
123
        clk_out5
124
        clk_out6
125
        clk_out7
126
        CLK_VALID
127
        NA
128
        daddr
129
        dclk
130
        den
131
        din
132
        1041
133
        1
134
        0.26666666666666666
135
        0.4
136
        0.4
137
        0.4
138
        0.4
139
        0.4
140
        dout
141
        drdy
142
        dwe
143
        0
144
        0
145
        0
146
        0
147
        0
148
        0
149
        0
150
        0
151
        FDBK_AUTO
152
        0800
153
        9990
154
        0
155
        Input Clock   Freq (MHz)    Input Jitter (UI)
156
        __primary_________200.000____________0.010
157
        no_secondary_input_clock 
158
        input_clk_stopped
159
        0
160
        Units_MHz
161
        No_Jitter
162
        locked
163
        03e8
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        3801
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        3be9
166
        false
167
        false
168
        false
169
        false
170
        false
171
        false
172
        false
173
        false
174
        OPTIMIZED
175
        5.250
176
        0.000
177
        FALSE
178
        5.0
179
        10.0
180
        26.250
181
        0.500
182
        0.000
183
        FALSE
184
        7
185
        0.500
186
        0.000
187
        FALSE
188
        1
189
        0.500
190
        0.000
191
        FALSE
192
        1
193
        0.500
194
        0.000
195
        FALSE
196
        FALSE
197
        1
198
        0.500
199
        0.000
200
        FALSE
201
        1
202
        0.500
203
        0.000
204
        FALSE
205
        1
206
        0.500
207
        0.000
208
        FALSE
209
        FALSE
210
        ZHOLD
211
        1
212
        None
213
        0.010
214
        0.010
215
        FALSE
216
        2
217
         Output     Output      Phase    Duty Cycle   Pk-to-Pk     Phase
218
          Clock     Freq (MHz)  (degrees)    (%)     Jitter (ps)  Error (ps)
219
        clk_out1____40.000______0.000______50.0______132.550_____87.375
220
        clk_out2___150.000______0.000______50.0______101.763_____87.375
221
        no_CLK_OUT3_output
222
        no_CLK_OUT4_output
223
        no_CLK_OUT5_output
224
        no_CLK_OUT6_output
225
        no_CLK_OUT7_output
226
        0
227
        0
228
        WAVEFORM
229
        UNKNOWN
230
        false
231
        false
232
        false
233
        false
234
        false
235
        OPTIMIZED
236
        1
237
        0.000
238
        1.000
239
        1
240
        0.500
241
        0.000
242
        1
243
        0.500
244
        0.000
245
        1
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        0.500
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        0.000
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        1
249
        0.500
250
        0.000
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        1
252
        0.500
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        0.000
254
        1
255
        0.500
256
        0.000
257
        CLKFBOUT
258
        SYSTEM_SYNCHRONOUS
259
        1
260
        No notes
261
        0.010
262
        power_down
263
        FFFF
264
        1
265
        clk_in1
266
        MMCM
267
        AUTO
268
        200.000
269
        0.010
270
        10.000
271
        Differential_clock_capable_pin
272
        psclk
273
        psdone
274
        psen
275
        psincdec
276
        100.0
277
        0
278
        reset
279
        100.000
280
        0.010
281
        10.000
282
        clk_in2
283
        Single_ended_clock_capable_pin
284
        CENTER_HIGH
285
        4000
286
        0.004
287
        STATUS
288
        11
289
        32
290
        100.0
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        100.0
292
        100.0
293
        100.0
294
        0
295
        0
296
        0
297
        0
298
        0
299
        0
300
        0
301
        0
302
        0
303
        0
304
        0
305
        1
306
        0
307
        0
308
        1
309
        0
310
        0
311
        0
312
        1
313
        0
314
        1
315
        0
316
        0
317
        0
318
        clk_40MHz
319
        MMCM
320
        false
321
        empty
322
        cddcdone
323
        cddcreq
324
        clkfb_in_n
325
        clkfb_in
326
        clkfb_in_p
327
        SINGLE
328
        clkfb_out_n
329
        clkfb_out
330
        clkfb_out_p
331
        clkfb_stopped
332
        50.0
333
        0.010
334
        100.0
335
        0.010
336
        BUFG
337
        132.550
338
        false
339
        87.375
340
        50.000
341
        40.000
342
        0.000
343
        1
344
        true
345
        BUFG
346
        101.763
347
        false
348
        87.375
349
        50.000
350
        150.000
351
        0.000
352
        1
353
        true
354
        BUFG
355
        0.0
356
        false
357
        0.0
358
        50.000
359
        100.000
360
        0.000
361
        1
362
        false
363
        BUFG
364
        0.0
365
        false
366
        0.0
367
        50.000
368
        100.000
369
        0.000
370
        1
371
        false
372
        BUFG
373
        0.0
374
        false
375
        0.0
376
        50.000
377
        100.000
378
        0.000
379
        1
380
        false
381
        BUFG
382
        0.0
383
        false
384
        0.0
385
        50.000
386
        100.000
387
        0.000
388
        1
389
        false
390
        BUFG
391
        0.0
392
        false
393
        0.0
394
        50.000
395
        100.000
396
        0.000
397
        1
398
        false
399
        600.000
400
        sys_diff_clock
401
        Custom
402
        clk_in_sel
403
        clk_out1
404
        false
405
        clk_out2
406
        false
407
        clk_out3
408
        false
409
        clk_out4
410
        false
411
        clk_out5
412
        false
413
        clk_out6
414
        false
415
        clk_out7
416
        false
417
        CLK_VALID
418
        auto
419
        clk_40MHz
420
        daddr
421
        dclk
422
        den
423
        Custom
424
        Custom
425
        din
426
        dout
427
        drdy
428
        dwe
429
        false
430
        false
431
        false
432
        false
433
        false
434
        false
435
        false
436
        false
437
        false
438
        FDBK_AUTO
439
        input_clk_stopped
440
        frequency
441
        Enable_AXI
442
        Units_MHz
443
        Units_UI
444
        UI
445
        No_Jitter
446
        locked
447
        OPTIMIZED
448
        5.250
449
        0.000
450
        false
451
        5.0
452
        10.0
453
        26.250
454
        0.500
455
        0.000
456
        false
457
        7
458
        0.500
459
        0.000
460
        false
461
        1
462
        0.500
463
        0.000
464
        false
465
        1
466
        0.500
467
        0.000
468
        false
469
        false
470
        1
471
        0.500
472
        0.000
473
        false
474
        1
475
        0.500
476
        0.000
477
        false
478
        1
479
        0.500
480
        0.000
481
        false
482
        false
483
        ZHOLD
484
        1
485
        None
486
        0.010
487
        0.010
488
        false
489
        2
490
        false
491
        false
492
        WAVEFORM
493
        false
494
        UNKNOWN
495
        OPTIMIZED
496
        4
497
        0.000
498
        10.000
499
        1
500
        0.500
501
        0.000
502
        1
503
        0.500
504
        0.000
505
        1
506
        0.500
507
        0.000
508
        1
509
        0.500
510
        0.000
511
        1
512
        0.500
513
        0.000
514
        1
515
        0.500
516
        0.000
517
        CLKFBOUT
518
        SYSTEM_SYNCHRONOUS
519
        1
520
        None
521
        0.010
522
        power_down
523
        1
524
        clk_in1
525
        MMCM
526
        mmcm_adv
527
        200.000
528
        0.010
529
        10.000
530
        Differential_clock_capable_pin
531
        psclk
532
        psdone
533
        psen
534
        psincdec
535
        100.0
536
        REL_PRIMARY
537
        Custom
538
        reset
539
        ACTIVE_HIGH
540
        100.000
541
        0.010
542
        10.000
543
        clk_in2
544
        Single_ended_clock_capable_pin
545
        CENTER_HIGH
546
        250
547
        0.004
548
        STATUS
549
        empty
550
        100.0
551
        100.0
552
        100.0
553
        100.0
554
        false
555
        false
556
        false
557
        false
558
        false
559
        false
560
        false
561
        true
562
        false
563
        false
564
        true
565
        false
566
        false
567
        false
568
        true
569
        false
570
        true
571
        false
572
        false
573
        false
574
        virtex7
575
        
576
        xc7vx485t
577
        ffg1761
578
        VHDL
579
        
580
        MIXED
581
        -2
582
        
583
        TRUE
584
        TRUE
585
        e3f8792d369a875e
586
        IP_Flow
587
        3
588
        TRUE
589
        .
590
        
591
        .
592
        2016.4
593
        OUT_OF_CONTEXT
594
      
595
      
596
        
597
          
598
            
599
            
600
            
601
            
602
            
603
            
604
            
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606
            
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618
    
619
  
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