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[/] [core1990_interlaken/] [trunk/] [gateware/] [sources/] [ip_cores/] [vc709/] [RX_FIFO.xci] - Blame information for rev 11

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Line No. Rev Author Line
1 11 N.Boukadid
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  xilinx.com
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  xci
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  unknown
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  1.0
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      RX_FIFO
10
      
11
      
12
        
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15
        100000000
16
        0.000
17
        
18
        
19
        100000000
20
        0.000
21
        1
22
        0
23
        0
24
        0
25
        
26
        1
27
        100000000
28
        0
29
        0
30
        0
31
        0
32
        0
33
        0
34
        0
35
        0
36
        0
37
        0
38
        1
39
        1
40
        1
41
        1
42
        1
43
        0.000
44
        AXI4LITE
45
        READ_WRITE
46
        0
47
        0
48
        0
49
        0
50
        0
51
        
52
        100000000
53
        0
54
        0
55
        0
56
        0
57
        undef
58
        0.000
59
        0
60
        0
61
        0
62
        0
63
        
64
        
65
        
66
        100000000
67
        0.000
68
        
69
        100000000
70
        0.000
71
        1
72
        0
73
        0
74
        0
75
        
76
        1
77
        100000000
78
        0
79
        0
80
        0
81
        0
82
        0
83
        0
84
        0
85
        0
86
        0
87
        0
88
        1
89
        1
90
        1
91
        1
92
        1
93
        0.000
94
        AXI4LITE
95
        READ_WRITE
96
        0
97
        0
98
        0
99
        0
100
        0
101
        
102
        100000000
103
        0
104
        0
105
        0
106
        0
107
        undef
108
        0.000
109
        0
110
        0
111
        0
112
        0
113
        
114
        
115
        
116
        100000000
117
        0.000
118
        0
119
        0
120
        0
121
        0
122
        0
123
        0
124
        0
125
        8
126
        1
127
        1
128
        1
129
        1
130
        4
131
        0
132
        32
133
        1
134
        1
135
        1
136
        64
137
        1
138
        8
139
        1
140
        1
141
        1
142
        1
143
        0
144
        0
145
        6
146
        BlankString
147
        71
148
        1
149
        32
150
        64
151
        1
152
        64
153
        2
154
        0
155
        71
156
        0
157
        1
158
        0
159
        0
160
        0
161
        0
162
        0
163
        0
164
        0
165
        0
166
        virtex7
167
        0
168
        0
169
        0
170
        1
171
        0
172
        0
173
        0
174
        0
175
        1
176
        0
177
        1
178
        0
179
        0
180
        0
181
        0
182
        1
183
        0
184
        1
185
        0
186
        0
187
        0
188
        0
189
        0
190
        0
191
        0
192
        0
193
        0
194
        0
195
        0
196
        0
197
        0
198
        0
199
        0
200
        0
201
        0
202
        0
203
        0
204
        0
205
        0
206
        1
207
        0
208
        0
209
        0
210
        1
211
        0
212
        0
213
        0
214
        2
215
        1
216
        1
217
        1
218
        1
219
        1
220
        1
221
        0
222
        0
223
        2
224
        BlankString
225
        1
226
        0
227
        0
228
        0
229
        1
230
        0
231
        512x72
232
        1kx18
233
        512x36
234
        1kx36
235
        512x36
236
        1kx36
237
        512x36
238
        4
239
        1022
240
        1022
241
        1022
242
        1022
243
        1022
244
        1022
245
        5
246
        2
247
        0
248
        0
249
        0
250
        0
251
        0
252
        0
253
        13
254
        1023
255
        1023
256
        1023
257
        1023
258
        1023
259
        1023
260
        12
261
        2
262
        0
263
        0
264
        0
265
        0
266
        0
267
        0
268
        0
269
        0
270
        6
271
        64
272
        1
273
        6
274
        0
275
        0
276
        0
277
        0
278
        0
279
        0
280
        0
281
        2
282
        0
283
        0
284
        0
285
        0
286
        1
287
        0
288
        0
289
        0
290
        0
291
        0
292
        0
293
        0
294
        0
295
        0
296
        0
297
        0
298
        0
299
        0
300
        0
301
        0
302
        0
303
        6
304
        64
305
        1024
306
        16
307
        1024
308
        16
309
        1024
310
        16
311
        1
312
        6
313
        10
314
        4
315
        10
316
        4
317
        10
318
        4
319
        1
320
        32
321
        0
322
        0
323
        false
324
        false
325
        false
326
        0
327
        0
328
        Slave_Interface_Clock_Enable
329
        Common_Clock
330
        RX_FIFO
331
        64
332
        false
333
        6
334
        false
335
        false
336
        0
337
        4
338
        1022
339
        1022
340
        1022
341
        1022
342
        1022
343
        1022
344
        5
345
        false
346
        false
347
        false
348
        false
349
        false
350
        false
351
        false
352
        false
353
        false
354
        Hard_ECC
355
        false
356
        false
357
        false
358
        false
359
        false
360
        false
361
        true
362
        false
363
        false
364
        true
365
        Data_FIFO
366
        Data_FIFO
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        Data_FIFO
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        Data_FIFO
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        Data_FIFO
370
        Data_FIFO
371
        Common_Clock_Block_RAM
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        Common_Clock_Block_RAM
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        Common_Clock_Block_RAM
374
        Common_Clock_Block_RAM
375
        Common_Clock_Block_RAM
376
        Common_Clock_Block_RAM
377
        Independent_Clocks_Distributed_RAM
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        0
379
        13
380
        1023
381
        1023
382
        1023
383
        1023
384
        1023
385
        1023
386
        12
387
        false
388
        false
389
        false
390
        0
391
        Native
392
        false
393
        false
394
        false
395
        false
396
        false
397
        false
398
        false
399
        false
400
        false
401
        false
402
        false
403
        false
404
        false
405
        false
406
        71
407
        64
408
        1024
409
        16
410
        1024
411
        16
412
        1024
413
        16
414
        false
415
        71
416
        64
417
        Embedded_Reg
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        false
419
        false
420
        Active_High
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        Active_High
422
        AXI4
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        Standard_FIFO
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        Multiple_Programmable_Empty_Threshold_Constants
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        No_Programmable_Empty_Threshold
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        No_Programmable_Empty_Threshold
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        No_Programmable_Empty_Threshold
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        No_Programmable_Empty_Threshold
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        No_Programmable_Empty_Threshold
430
        No_Programmable_Empty_Threshold
431
        Multiple_Programmable_Full_Threshold_Constants
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        No_Programmable_Full_Threshold
433
        No_Programmable_Full_Threshold
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        No_Programmable_Full_Threshold
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        No_Programmable_Full_Threshold
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        No_Programmable_Full_Threshold
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        No_Programmable_Full_Threshold
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        READ_WRITE
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        0
440
        1
441
        false
442
        6
443
        Fully_Registered
444
        Fully_Registered
445
        Fully_Registered
446
        Fully_Registered
447
        Fully_Registered
448
        Fully_Registered
449
        true
450
        Asynchronous_Reset
451
        false
452
        1
453
        0
454
        0
455
        1
456
        1
457
        4
458
        false
459
        false
460
        Active_High
461
        Active_High
462
        true
463
        false
464
        false
465
        false
466
        true
467
        Active_High
468
        0
469
        false
470
        Active_High
471
        1
472
        false
473
        6
474
        false
475
        FIFO
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        false
477
        false
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        false
479
        false
480
        FIFO
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        FIFO
482
        2
483
        2
484
        false
485
        FIFO
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        FIFO
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        FIFO
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        virtex7
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490
        xc7vx690t
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        ffg1761
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        VHDL
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        MIXED
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        -2
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        TRUE
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        TRUE
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        IP_Flow
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        2
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        TRUE
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        .
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        .
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        2018.1
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        OUT_OF_CONTEXT
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