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<P><table class="ttop"><th class="tpre"><a href="23_Listing_of_register_file.vhd.html">Previous Lesson</a></th><th class="ttop"><a href="toc.html">Table of Content</a></th><th class="tnxt"><a href="25_Listing_of_status_reg.vhd.html">Next Lesson</a></th></table>
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<H1><A NAME="section_1">24 LISTING OF segment7.vhd</A></H1>
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<pre class="vhdl">
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1 -------------------------------------------------------------------------------
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2 --
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3 -- Copyright (C) 2009, 2010 Dr. Juergen Sauermann
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4 --
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5 -- This code is free software: you can redistribute it and/or modify
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6 -- it under the terms of the GNU General Public License as published by
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7 -- the Free Software Foundation, either version 3 of the License, or
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8 -- (at your option) any later version.
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9 --
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10 -- This code is distributed in the hope that it will be useful,
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11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
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12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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13 -- GNU General Public License for more details.
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14 --
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15 -- You should have received a copy of the GNU General Public License
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16 -- along with this code (see the file named COPYING).
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17 -- If not, see http://www.gnu.org/licenses/.
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18 --
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19 -------------------------------------------------------------------------------
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20 -------------------------------------------------------------------------------
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21 --
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22 -- Module Name: segment7 - Behavioral
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23 -- Create Date: 12:52:16 11/11/2009
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24 -- Description: a 7 segment LED display interface.
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25 --
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26 -------------------------------------------------------------------------------
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27 --
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28 library IEEE;
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29 use IEEE.STD_LOGIC_1164.ALL;
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30 use IEEE.STD_LOGIC_ARITH.ALL;
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31 use IEEE.STD_LOGIC_UNSIGNED.ALL;
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32
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33 entity segment7 is
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34 port ( I_CLK : in std_logic;
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35
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36 I_CLR : in std_logic;
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37 I_OPC : in std_logic_vector(15 downto 0);
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38 I_PC : in std_logic_vector(15 downto 0);
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39
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40 Q_7_SEGMENT : out std_logic_vector( 6 downto 0));
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41 end segment7;
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42
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43 -- Signal Loc Alt
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44 ---------------------------
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45 -- SEG_LED(0) V3 A
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46 -- SEG_LED(1) V4 B
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47 -- SEG_LED(2) W3 C
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48 -- SEG_LED(3) T4 D
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49 -- SEG_LED(4) T3 E
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50 -- SEG_LED(5) U3 F
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51 -- SEG_LED(6) U4 G
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52 --
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53 architecture Behavioral of segment7 is
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54
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55 function lmap(VAL: std_logic_vector( 3 downto 0))
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56 return std_logic_vector is
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57 begin
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58 case VAL is -- 6543210
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59 when "0000" => return "0111111"; -- 0
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60 when "0001" => return "0000110"; -- 1
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61 when "0010" => return "1011011"; -- 2
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62 when "0011" => return "1001111"; -- 3
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63 when "0100" => return "1100110"; -- 4 ----A---- ----0----
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64 when "0101" => return "1101101"; -- 5 | | | |
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65 when "0110" => return "1111101"; -- 6 F B 5 1
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66 when "0111" => return "0000111"; -- 7 | | | |
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67 when "1000" => return "1111111"; -- 8 +---G---+ +---6---+
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68 when "1001" => return "1101111"; -- 9 | | | |
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69 when "1010" => return "1110111"; -- A E C 4 2
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70 when "1011" => return "1111100"; -- b | | | |
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71 when "1100" => return "0111001"; -- C ----D---- ----3----
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72 when "1101" => return "1011110"; -- d
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73 when "1110" => return "1111001"; -- E
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74 when others => return "1110001"; -- F
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75 end case;
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76 end;
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77
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78 signal L_CNT : std_logic_vector(27 downto 0);
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79 signal L_OPC : std_logic_vector(15 downto 0);
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80 signal L_PC : std_logic_vector(15 downto 0);
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81 signal L_POS : std_logic_vector( 3 downto 0);
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82
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83 begin
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84
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85 process(I_CLK) -- 20 MHz
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86 begin
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87 if (rising_edge(I_CLK)) then
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88 if (I_CLR = '1') then
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89 L_POS <= "0000";
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90 L_CNT <= X"0000000";
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91 Q_7_SEGMENT <= "1111111";
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92 else
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93 L_CNT <= L_CNT + X"0000001";
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94 if (L_CNT = X"0C00000") then
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95 Q_7_SEGMENT <= "1111111"; -- blank
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96 elsif (L_CNT = X"1000000") then
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97 L_CNT <= X"0000000";
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98 L_POS <= L_POS + "0001";
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99 case L_POS is
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100 when "0000" => -- blank
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101 Q_7_SEGMENT <= "1111111";
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102 when "0001" =>
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103 L_PC <= I_PC; -- sample PC
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104 L_OPC <= I_OPC; -- sample OPC
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105 Q_7_SEGMENT <= not lmap(L_PC(15 downto 12));
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106 when "0010" =>
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107 Q_7_SEGMENT <= not lmap(L_PC(11 downto 8));
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108 when "0011" =>
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109 Q_7_SEGMENT <= not lmap(L_PC( 7 downto 4));
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110 when "0100" =>
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111 Q_7_SEGMENT <= not lmap(L_PC( 3 downto 0));
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112 when "0101" => -- minus
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113 Q_7_SEGMENT <= "0111111";
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114 when "0110" =>
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115 Q_7_SEGMENT <= not lmap(L_OPC(15 downto 12));
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116 when "0111" =>
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117 Q_7_SEGMENT <= not lmap(L_OPC(11 downto 8));
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118 when "1000" =>
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119 Q_7_SEGMENT <= not lmap(L_OPC( 7 downto 4));
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120 when "1001" =>
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121 Q_7_SEGMENT <= not lmap(L_OPC( 3 downto 0));
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122 L_POS <= "0000";
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123 when others =>
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124 L_POS <= "0000";
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125 end case;
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126 end if;
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127 end if;
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128 end if;
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129 end process;
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130
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131 end Behavioral;
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132
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<pre class="filename">
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src/segment7.vhd
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</pre></pre>
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<P>
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<P><hr><BR>
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<table class="ttop"><th class="tpre"><a href="23_Listing_of_register_file.vhd.html">Previous Lesson</a></th><th class="ttop"><a href="toc.html">Table of Content</a></th><th class="tnxt"><a href="25_Listing_of_status_reg.vhd.html">Next Lesson</a></th></table>
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