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# Copyright (c) 2018, Marcelo Samsoniuk

# All rights reserved.

#

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# modification, are permitted provided that the following conditions are met:

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# * Redistributions of source code must retain the above copyright notice, this

#   list of conditions and the following disclaimer.

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#NET "CLK" TNM_NET = CLK;

# without cache controller

#TIMESPEC TS_CLK = PERIOD "CLK" 75MHz HIGH 50%;

# with cache controller

#TIMESPEC TS_CLK = PERIOD "CLK" 75MHz HIGH 50%;

# Digilent Spartan3 S200

NET XCLK            LOC = T9 | PERIOD = 50MHz HIGH 50%;

#NET XCLK            LOC = K15 | PERIOD = 66MHz HIGH 50%;

#NET XCLK            LOC = V10 | PERIOD = 40MHz HIGH 50%;

NET XRES            LOC = M13  | PULLDOWN;

NET UART_RXD        LOC = T13  | PULLUP;

NET UART_TXD        LOC = R13;

NET LED[3]          LOC = K12;

NET LED[2]          LOC = P14;

NET LED[1]          LOC = L12;

NET LED[0]          LOC = N14;

NET DEBUG[3]        LOC = P13; # J4-1

NET DEBUG[2]        LOC = N12; # J4-2

NET DEBUG[1]        LOC = P12; # J4-3

NET DEBUG[0]        LOC = P11; # J4-4