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[/] [dma_ahb/] [trunk/] [src/] [dma_ahb32/] [dma_ahb32_core0_ch_calc.v] - Blame information for rev 2

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1 2 eyalhoc
//---------------------------------------------------------
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//-- File generated by RobustVerilog parser
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//-- Version: 1.0
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//-- Invoked Fri Mar 25 23:31:24 2011
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//--
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//-- Source file: dma_ch_calc.v
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//---------------------------------------------------------
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module dma_ahb32_core0_ch_calc(clk,reset,load_in_prog,load_req_in_prog,load_addr,ch_update,ch_end,ch_end_flush,go_next_line,burst_start,incr,wr_cmd_pending,outs_empty,burst_max_size,start_addr,frame_width,x_size,x_remain,fifo_wr_ready,fifo_remain,burst_last,burst_addr,burst_size,burst_ready,single,joint_ready_out,joint_ready_in,joint_line_req_in,joint_line_req_out,joint_burst_req_in,joint_burst_req_out,joint_line_req_clr,joint,page_cross,joint_cross,joint_flush,joint_flush_in);
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   parameter                READ = 0;
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   parameter             SINGLE_SIZE   = 4;
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   input             clk;
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   input             reset;
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   input             load_in_prog;
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   input             load_req_in_prog;
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   input [32-1:0]    load_addr;
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   input             ch_update;
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   input             ch_end;
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   input             ch_end_flush;
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   input             go_next_line;
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   input             burst_start;
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   input             incr;
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   input             wr_cmd_pending;
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   input             outs_empty;
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   input [7-1:0]   burst_max_size;
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   input [32-1:0]    start_addr;
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   input [`FRAME_BITS-1:0]  frame_width;
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   input [`X_BITS-1:0]         x_size;
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   input [10-1:0]    x_remain;
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   input             fifo_wr_ready;
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   input [5:0]         fifo_remain;
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   output             burst_last;
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   output [32-1:0]   burst_addr;
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   output [7-1:0]  burst_size;
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   output             burst_ready;
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   output             single;
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   output             joint_ready_out;
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   input             joint_ready_in;
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   input             joint_line_req_in;
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   output             joint_line_req_out;
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   input             joint_burst_req_in;
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   output             joint_burst_req_out;
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   input             joint_line_req_clr;
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   input             joint;
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   input             page_cross;
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   input             joint_cross;
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   output             joint_flush;
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   input             joint_flush_in;
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   wire             ch_update_d;
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   wire             ch_update_d2;
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   wire             ch_update_d3;
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   //outputs of calc_addr
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   wire [32-1:0]     burst_addr;
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   //outputs of calc_size
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   wire [7-1:0]    burst_size;
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   reg                 single;
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   prgen_delay #(1) delay_calc0(.clk(clk), .reset(reset), .din(ch_update), .dout(ch_update_d));
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   prgen_delay #(1) delay_calc1(.clk(clk), .reset(reset), .din(ch_update_d), .dout(ch_update_d2));
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   prgen_delay #(1) delay_calc2(.clk(clk), .reset(reset), .din(ch_update_d2), .dout(ch_update_d3));
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   always @(posedge clk or posedge reset)
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     if (reset)
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       single <= #1 1'b0;
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     else if (burst_start)
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       single <= #1 (burst_size <= SINGLE_SIZE);
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   dma_ahb32_core0_ch_calc_addr
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   dma_ahb32_ch_calc_addr (
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            .clk(clk),
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            .reset(reset),
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            .ch_update_d(ch_update_d),
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            .load_in_prog(load_in_prog),
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            .load_addr(load_addr),
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            .go_next_line(go_next_line),
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            .burst_start(burst_start),
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            .incr(incr),
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            .start_addr(start_addr),
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            .frame_width(frame_width),
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            .x_size(x_size),
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            .burst_size(burst_size),
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            .burst_addr(burst_addr)
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            );
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   dma_ahb32_core0_ch_calc_size #(.READ(READ))
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   dma_ahb32_ch_calc_size (
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            .clk(clk),
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            .reset(reset),
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            .ch_update(ch_update),
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            .ch_update_d(ch_update_d),
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            .ch_update_d2(ch_update_d2),
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            .ch_update_d3(ch_update_d3),
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            .ch_end(ch_end),
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            .ch_end_flush(ch_end_flush),
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            .joint_line_req_clr(joint_line_req_clr),
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            .wr_cmd_pending(wr_cmd_pending),
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            .outs_empty(outs_empty),
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            .load_in_prog(load_in_prog),
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            .load_req_in_prog(load_req_in_prog),
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            .burst_start(burst_start),
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            .burst_addr(burst_addr),
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            .burst_max_size(burst_max_size),
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            .x_remain(x_remain),
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            .fifo_wr_ready(fifo_wr_ready),
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            .fifo_remain(fifo_remain),
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            .burst_size(burst_size),
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            .burst_ready(burst_ready),
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            .burst_last(burst_last),
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            .joint_ready_out(joint_ready_out),
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            .joint_ready_in(joint_ready_in),
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            .joint_line_req_in(joint_line_req_in),
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            .joint_line_req_out(joint_line_req_out),
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            .joint_burst_req_in(joint_burst_req_in),
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            .joint_burst_req_out(joint_burst_req_out),
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            .joint(joint),
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            .page_cross(page_cross),
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            .joint_cross(joint_cross),
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            .joint_flush(joint_flush),
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            .joint_flush_in(joint_flush_in)
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            );
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endmodule
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