| 1 |
2 |
eyalhoc |
//---------------------------------------------------------
|
| 2 |
|
|
//-- File generated by RobustVerilog parser
|
| 3 |
|
|
//-- Version: 1.0
|
| 4 |
|
|
//-- Invoked Fri Mar 25 23:31:23 2011
|
| 5 |
|
|
//--
|
| 6 |
|
|
//-- Source file: dma_core_channels.v
|
| 7 |
|
|
//---------------------------------------------------------
|
| 8 |
|
|
|
| 9 |
|
|
|
| 10 |
|
|
|
| 11 |
|
|
module dma_ahb32_core0_channels(clk,reset,scan_en,pclk,clken,pclken,psel,penable,paddr,pwrite,pwdata,prdata,pslverr,periph_tx_req,periph_tx_clr,periph_rx_req,periph_rx_clr,rd_clr_valid,wr_clr_valid,rd_clr,rd_clr_load,wr_clr,rd_cmd_split,rd_cmd_line,rd_cmd_num,wr_cmd_split,wr_cmd_pending,wr_cmd_num,rd_clr_stall,wr_clr_stall,load_wr,load_wr_num,load_wr_cycle,load_wdata,rd_ch_num,load_req_in_prog,wr_ch_num,wr_last_cmd,rd_slverr,rd_decerr,wr_slverr,wr_decerr,rd_ch_num_resp,wr_ch_num_resp,wr_clr_last,ch_int_all_proc,ch_start,ch_idle,ch_active,ch_rd_active,ch_wr_active,rd_line_cmd,wr_line_cmd,rd_go_next_line,wr_go_next_line,timeout_aw,timeout_w,timeout_ar,timeout_num_aw,timeout_num_w,timeout_num_ar,wdt_timeout,wdt_ch_num,ch_fifo_wr_num,rd_transfer_num,rd_burst_start,rd_transfer,rd_transfer_size,rd_clr_line,rd_clr_line_num,fifo_rd,fifo_rsize,fifo_rd_valid,fifo_rdata,fifo_wr_ready,ch_rd_ready,rd_burst_addr,rd_burst_size,rd_tokens,rd_cmd_port,rd_periph_delay,ch_fifo_rd_num,wr_transfer_num,wr_burst_start,wr_transfer,wr_transfer_size,wr_next_size,wr_clr_line,wr_clr_line_num,fifo_wr,fifo_wdata,fifo_wsize,ch_wr_ready,wr_burst_addr,wr_burst_size,wr_tokens,wr_cmd_port,wr_periph_delay,joint_mode,joint_remote,rd_page_cross,wr_page_cross,joint_in_prog,joint_not_in_prog,joint_mux_in_prog,ch_joint_req);
|
| 12 |
|
|
|
| 13 |
|
|
input clk;
|
| 14 |
|
|
input reset;
|
| 15 |
|
|
input scan_en;
|
| 16 |
|
|
|
| 17 |
|
|
input pclk;
|
| 18 |
|
|
input clken;
|
| 19 |
|
|
input pclken;
|
| 20 |
|
|
input psel;
|
| 21 |
|
|
input penable;
|
| 22 |
|
|
input [10:0] paddr;
|
| 23 |
|
|
input pwrite;
|
| 24 |
|
|
input [31:0] pwdata;
|
| 25 |
|
|
output [31:0] prdata;
|
| 26 |
|
|
output pslverr;
|
| 27 |
|
|
|
| 28 |
|
|
input [31:1] periph_tx_req;
|
| 29 |
|
|
output [31:1] periph_tx_clr;
|
| 30 |
|
|
input [31:1] periph_rx_req;
|
| 31 |
|
|
output [31:1] periph_rx_clr;
|
| 32 |
|
|
output rd_clr_valid;
|
| 33 |
|
|
output wr_clr_valid;
|
| 34 |
|
|
input rd_clr;
|
| 35 |
|
|
input rd_clr_load;
|
| 36 |
|
|
input wr_clr;
|
| 37 |
|
|
input rd_cmd_split;
|
| 38 |
|
|
input rd_cmd_line;
|
| 39 |
|
|
input [2:0] rd_cmd_num;
|
| 40 |
|
|
input wr_cmd_split;
|
| 41 |
|
|
input wr_cmd_pending;
|
| 42 |
|
|
input [2:0] wr_cmd_num;
|
| 43 |
|
|
output rd_clr_stall;
|
| 44 |
|
|
output wr_clr_stall;
|
| 45 |
|
|
|
| 46 |
|
|
input load_wr;
|
| 47 |
|
|
input [2:0] load_wr_num;
|
| 48 |
|
|
input [1:0] load_wr_cycle;
|
| 49 |
|
|
input [32-1:0] load_wdata;
|
| 50 |
|
|
|
| 51 |
|
|
input [2:0] rd_ch_num;
|
| 52 |
|
|
output load_req_in_prog;
|
| 53 |
|
|
|
| 54 |
|
|
input [2:0] wr_ch_num;
|
| 55 |
|
|
output wr_last_cmd;
|
| 56 |
|
|
|
| 57 |
|
|
input rd_slverr;
|
| 58 |
|
|
input rd_decerr;
|
| 59 |
|
|
input wr_slverr;
|
| 60 |
|
|
input wr_decerr;
|
| 61 |
|
|
input [2:0] rd_ch_num_resp;
|
| 62 |
|
|
input [2:0] wr_ch_num_resp;
|
| 63 |
|
|
input wr_clr_last;
|
| 64 |
|
|
output [8*1-1:0] ch_int_all_proc;
|
| 65 |
|
|
input [7:0] ch_start;
|
| 66 |
|
|
output [7:0] ch_idle;
|
| 67 |
|
|
output [7:0] ch_active;
|
| 68 |
|
|
output [7:0] ch_rd_active;
|
| 69 |
|
|
output [7:0] ch_wr_active;
|
| 70 |
|
|
output rd_line_cmd;
|
| 71 |
|
|
output wr_line_cmd;
|
| 72 |
|
|
output rd_go_next_line;
|
| 73 |
|
|
output wr_go_next_line;
|
| 74 |
|
|
|
| 75 |
|
|
input timeout_aw;
|
| 76 |
|
|
input timeout_w;
|
| 77 |
|
|
input timeout_ar;
|
| 78 |
|
|
input [2:0] timeout_num_aw;
|
| 79 |
|
|
input [2:0] timeout_num_w;
|
| 80 |
|
|
input [2:0] timeout_num_ar;
|
| 81 |
|
|
input wdt_timeout;
|
| 82 |
|
|
input [2:0] wdt_ch_num;
|
| 83 |
|
|
|
| 84 |
|
|
input [2:0] ch_fifo_wr_num;
|
| 85 |
|
|
input [2:0] rd_transfer_num;
|
| 86 |
|
|
input rd_burst_start;
|
| 87 |
|
|
input rd_transfer;
|
| 88 |
|
|
input [3-1:0] rd_transfer_size;
|
| 89 |
|
|
input rd_clr_line;
|
| 90 |
|
|
input [2:0] rd_clr_line_num;
|
| 91 |
|
|
input fifo_rd;
|
| 92 |
|
|
input [3-1:0] fifo_rsize;
|
| 93 |
|
|
output fifo_rd_valid;
|
| 94 |
|
|
output [32-1:0] fifo_rdata;
|
| 95 |
|
|
output fifo_wr_ready;
|
| 96 |
|
|
output [7:0] ch_rd_ready;
|
| 97 |
|
|
output [32-1:0] rd_burst_addr;
|
| 98 |
|
|
output [7-1:0] rd_burst_size;
|
| 99 |
|
|
output [`TOKEN_BITS-1:0] rd_tokens;
|
| 100 |
|
|
output rd_cmd_port;
|
| 101 |
|
|
|
| 102 |
|
|
output [`DELAY_BITS-1:0] rd_periph_delay;
|
| 103 |
|
|
|
| 104 |
|
|
input [2:0] ch_fifo_rd_num;
|
| 105 |
|
|
input [2:0] wr_transfer_num;
|
| 106 |
|
|
input wr_burst_start;
|
| 107 |
|
|
input wr_transfer;
|
| 108 |
|
|
input [3-1:0] wr_transfer_size;
|
| 109 |
|
|
input [3-1:0] wr_next_size;
|
| 110 |
|
|
input wr_clr_line;
|
| 111 |
|
|
input [2:0] wr_clr_line_num;
|
| 112 |
|
|
input fifo_wr;
|
| 113 |
|
|
input [32-1:0] fifo_wdata;
|
| 114 |
|
|
input [3-1:0] fifo_wsize;
|
| 115 |
|
|
output [7:0] ch_wr_ready;
|
| 116 |
|
|
output [32-1:0] wr_burst_addr;
|
| 117 |
|
|
output [7-1:0] wr_burst_size;
|
| 118 |
|
|
output [`TOKEN_BITS-1:0] wr_tokens;
|
| 119 |
|
|
output wr_cmd_port;
|
| 120 |
|
|
output [`DELAY_BITS-1:0] wr_periph_delay;
|
| 121 |
|
|
|
| 122 |
|
|
input joint_mode;
|
| 123 |
|
|
input joint_remote;
|
| 124 |
|
|
input rd_page_cross;
|
| 125 |
|
|
input wr_page_cross;
|
| 126 |
|
|
output joint_in_prog;
|
| 127 |
|
|
output joint_not_in_prog;
|
| 128 |
|
|
output joint_mux_in_prog;
|
| 129 |
|
|
output [7:0] ch_joint_req;
|
| 130 |
|
|
|
| 131 |
|
|
|
| 132 |
|
|
|
| 133 |
|
|
parameter CH0 = 0;
|
| 134 |
|
|
parameter CH1 = 1;
|
| 135 |
|
|
parameter CH2 = 2;
|
| 136 |
|
|
parameter CH3 = 3;
|
| 137 |
|
|
parameter CH4 = 4;
|
| 138 |
|
|
parameter CH5 = 5;
|
| 139 |
|
|
parameter CH6 = 6;
|
| 140 |
|
|
parameter CH7 = 7;
|
| 141 |
|
|
|
| 142 |
|
|
|
| 143 |
|
|
//apb buses
|
| 144 |
|
|
wire [7:0] ch_psel;
|
| 145 |
|
|
wire [7:0] ch_pslverr;
|
| 146 |
|
|
wire [32*8-1:0] ch_prdata;
|
| 147 |
|
|
|
| 148 |
|
|
wire [7:0] ch_joint_end;
|
| 149 |
|
|
wire [7:0] ch_joint_in_prog;
|
| 150 |
|
|
wire [7:0] ch_joint_not_in_prog;
|
| 151 |
|
|
wire [7:0] ch_joint_mux_in_prog;
|
| 152 |
|
|
|
| 153 |
|
|
wire [7:0] ch_rd_page_cross;
|
| 154 |
|
|
wire [7:0] ch_wr_page_cross;
|
| 155 |
|
|
|
| 156 |
|
|
//axim signals
|
| 157 |
|
|
wire [7:0] ch_load_wr;
|
| 158 |
|
|
wire [7:0] ch_rd_clr_line;
|
| 159 |
|
|
wire [7:0] ch_rd_slverr;
|
| 160 |
|
|
wire [7:0] ch_rd_decerr;
|
| 161 |
|
|
wire [7:0] ch_rd_clr;
|
| 162 |
|
|
wire [7:0] ch_rd_clr_load;
|
| 163 |
|
|
wire [7:0] ch_rd_transfer;
|
| 164 |
|
|
wire [7:0] ch_rd_clr_stall;
|
| 165 |
|
|
wire [7:0] ch_rd_cmd_split;
|
| 166 |
|
|
wire [7:0] ch_rd_cmd_line;
|
| 167 |
|
|
|
| 168 |
|
|
wire [7:0] ch_wr_clr_line;
|
| 169 |
|
|
wire [7:0] ch_wr_slverr;
|
| 170 |
|
|
wire [7:0] ch_wr_decerr;
|
| 171 |
|
|
wire [7:0] ch_wr_clr_last;
|
| 172 |
|
|
wire [7:0] ch_wr_clr;
|
| 173 |
|
|
wire [7:0] ch_load_req_in_prog;
|
| 174 |
|
|
wire [7:0] ch_wr_last_cmd;
|
| 175 |
|
|
wire [7:0] ch_rd_line_cmd;
|
| 176 |
|
|
wire [7:0] ch_wr_line_cmd;
|
| 177 |
|
|
wire [7:0] ch_rd_go_next_line;
|
| 178 |
|
|
wire [7:0] ch_wr_go_next_line;
|
| 179 |
|
|
wire [7:0] ch_wr_transfer;
|
| 180 |
|
|
wire [7:0] ch_wr_clr_stall;
|
| 181 |
|
|
wire [7:0] ch_wr_cmd_split;
|
| 182 |
|
|
wire [7:0] ch_timeout_aw;
|
| 183 |
|
|
wire [7:0] ch_timeout_w;
|
| 184 |
|
|
wire [7:0] ch_timeout_ar;
|
| 185 |
|
|
wire [7:0] ch_wdt_timeout;
|
| 186 |
|
|
|
| 187 |
|
|
//rd ctrl signals
|
| 188 |
|
|
wire [7:0] ch_rd_burst_start;
|
| 189 |
|
|
wire [8*32-1:0] ch_rd_burst_addr;
|
| 190 |
|
|
wire [8*7-1:0] ch_rd_burst_size;
|
| 191 |
|
|
wire [8*`TOKEN_BITS-1:0] ch_rd_tokens;
|
| 192 |
|
|
wire [7:0] ch_rd_port_num;
|
| 193 |
|
|
wire [8*`DELAY_BITS-1:0] ch_rd_periph_delay;
|
| 194 |
|
|
wire [7:0] ch_rd_clr_valid;
|
| 195 |
|
|
|
| 196 |
|
|
//wr ctrl signals
|
| 197 |
|
|
wire [7:0] ch_wr_burst_start;
|
| 198 |
|
|
wire [8*32-1:0] ch_wr_burst_addr;
|
| 199 |
|
|
wire [8*7-1:0] ch_wr_burst_size;
|
| 200 |
|
|
wire [8*`TOKEN_BITS-1:0] ch_wr_tokens;
|
| 201 |
|
|
wire [7:0] ch_wr_port_num;
|
| 202 |
|
|
wire [8*`DELAY_BITS-1:0] ch_wr_periph_delay;
|
| 203 |
|
|
wire [7:0] ch_wr_clr_valid;
|
| 204 |
|
|
|
| 205 |
|
|
//CLR buses
|
| 206 |
|
|
wire [8*31-1:0] ch_periph_rx_clr;
|
| 207 |
|
|
wire [8*31-1:0] ch_periph_tx_clr;
|
| 208 |
|
|
|
| 209 |
|
|
//FIFO signals
|
| 210 |
|
|
wire [7:0] ch_fifo_wr;
|
| 211 |
|
|
wire [7:0] ch_fifo_rd;
|
| 212 |
|
|
wire [7:0] ch_fifo_rd_valid;
|
| 213 |
|
|
wire [8*32-1:0] ch_fifo_rdata;
|
| 214 |
|
|
wire [7:0] ch_fifo_wr_ready;
|
| 215 |
|
|
|
| 216 |
|
|
wire [7:0] ch_wr_cmd_pending;
|
| 217 |
|
|
|
| 218 |
|
|
|
| 219 |
|
|
dma_ahb32_core0_channels_apb_mux dma_ahb32_channels_apb_mux (
|
| 220 |
|
|
.clk(pclk),
|
| 221 |
|
|
.reset(reset),
|
| 222 |
|
|
.pclken(pclken),
|
| 223 |
|
|
.psel(psel),
|
| 224 |
|
|
.penable(penable),
|
| 225 |
|
|
.paddr(paddr[10:8]),
|
| 226 |
|
|
.prdata(prdata),
|
| 227 |
|
|
.pslverr(pslverr),
|
| 228 |
|
|
.ch_psel(ch_psel),
|
| 229 |
|
|
.ch_prdata(ch_prdata),
|
| 230 |
|
|
.ch_pslverr(ch_pslverr)
|
| 231 |
|
|
);
|
| 232 |
|
|
|
| 233 |
|
|
|
| 234 |
|
|
dma_ahb32_core0_channels_mux
|
| 235 |
|
|
dma_ahb32_channels_mux (
|
| 236 |
|
|
.ch_joint_in_prog(ch_joint_in_prog),
|
| 237 |
|
|
.ch_joint_not_in_prog(ch_joint_not_in_prog),
|
| 238 |
|
|
.ch_joint_mux_in_prog(ch_joint_mux_in_prog),
|
| 239 |
|
|
.joint_in_prog(joint_in_prog),
|
| 240 |
|
|
.joint_not_in_prog(joint_not_in_prog),
|
| 241 |
|
|
.joint_mux_in_prog(joint_mux_in_prog),
|
| 242 |
|
|
|
| 243 |
|
|
.ch_rd_page_cross(ch_rd_page_cross),
|
| 244 |
|
|
.ch_wr_page_cross(ch_wr_page_cross),
|
| 245 |
|
|
.rd_page_cross(rd_page_cross),
|
| 246 |
|
|
.wr_page_cross(wr_page_cross),
|
| 247 |
|
|
|
| 248 |
|
|
.ch_wr_cmd_pending(ch_wr_cmd_pending),
|
| 249 |
|
|
.wr_cmd_pending(wr_cmd_pending),
|
| 250 |
|
|
|
| 251 |
|
|
//data
|
| 252 |
|
|
.fifo_rdata(fifo_rdata),
|
| 253 |
|
|
.ch_fifo_rdata(ch_fifo_rdata),
|
| 254 |
|
|
.fifo_rd_valid(fifo_rd_valid),
|
| 255 |
|
|
.ch_fifo_rd_valid(ch_fifo_rd_valid),
|
| 256 |
|
|
|
| 257 |
|
|
//periph
|
| 258 |
|
|
.periph_rx_clr(periph_rx_clr),
|
| 259 |
|
|
.ch_periph_rx_clr(ch_periph_rx_clr),
|
| 260 |
|
|
.periph_tx_clr(periph_tx_clr),
|
| 261 |
|
|
.ch_periph_tx_clr(ch_periph_tx_clr),
|
| 262 |
|
|
|
| 263 |
|
|
//axim timeout
|
| 264 |
|
|
.timeout_aw(timeout_aw),
|
| 265 |
|
|
.timeout_w(timeout_w),
|
| 266 |
|
|
.timeout_ar(timeout_ar),
|
| 267 |
|
|
.timeout_num_aw(timeout_num_aw),
|
| 268 |
|
|
.timeout_num_w(timeout_num_w),
|
| 269 |
|
|
.timeout_num_ar(timeout_num_ar),
|
| 270 |
|
|
.wdt_timeout(wdt_timeout),
|
| 271 |
|
|
.wdt_ch_num(wdt_ch_num),
|
| 272 |
|
|
|
| 273 |
|
|
.ch_timeout_aw(ch_timeout_aw),
|
| 274 |
|
|
.ch_timeout_w(ch_timeout_w),
|
| 275 |
|
|
.ch_timeout_ar(ch_timeout_ar),
|
| 276 |
|
|
.ch_wdt_timeout(ch_wdt_timeout),
|
| 277 |
|
|
|
| 278 |
|
|
//rd cmd
|
| 279 |
|
|
.rd_ch_num(rd_ch_num),
|
| 280 |
|
|
.rd_cmd_num(rd_cmd_num),
|
| 281 |
|
|
|
| 282 |
|
|
.load_req_in_prog(load_req_in_prog),
|
| 283 |
|
|
.rd_line_cmd(rd_line_cmd),
|
| 284 |
|
|
.rd_go_next_line(rd_go_next_line),
|
| 285 |
|
|
.rd_burst_start(rd_burst_start),
|
| 286 |
|
|
.rd_burst_addr(rd_burst_addr),
|
| 287 |
|
|
.rd_burst_size(rd_burst_size),
|
| 288 |
|
|
.rd_tokens(rd_tokens),
|
| 289 |
|
|
.rd_cmd_port(rd_cmd_port),
|
| 290 |
|
|
.rd_periph_delay(rd_periph_delay),
|
| 291 |
|
|
.rd_clr_valid(rd_clr_valid),
|
| 292 |
|
|
.rd_cmd_split(rd_cmd_split),
|
| 293 |
|
|
.rd_cmd_line(rd_cmd_line),
|
| 294 |
|
|
.rd_clr_stall(rd_clr_stall),
|
| 295 |
|
|
|
| 296 |
|
|
.ch_load_req_in_prog(ch_load_req_in_prog),
|
| 297 |
|
|
.ch_rd_line_cmd(ch_rd_line_cmd),
|
| 298 |
|
|
.ch_rd_go_next_line(ch_rd_go_next_line),
|
| 299 |
|
|
.ch_rd_burst_start(ch_rd_burst_start),
|
| 300 |
|
|
.ch_rd_burst_addr(ch_rd_burst_addr),
|
| 301 |
|
|
.ch_rd_burst_size(ch_rd_burst_size),
|
| 302 |
|
|
.ch_rd_tokens(ch_rd_tokens),
|
| 303 |
|
|
.ch_rd_port_num(ch_rd_port_num),
|
| 304 |
|
|
.ch_rd_periph_delay(ch_rd_periph_delay),
|
| 305 |
|
|
.ch_rd_clr_valid(ch_rd_clr_valid),
|
| 306 |
|
|
.ch_rd_cmd_split(ch_rd_cmd_split),
|
| 307 |
|
|
.ch_rd_cmd_line(ch_rd_cmd_line),
|
| 308 |
|
|
.ch_rd_clr_stall(ch_rd_clr_stall),
|
| 309 |
|
|
|
| 310 |
|
|
//rd data - load cmd
|
| 311 |
|
|
.load_wr_num(load_wr_num),
|
| 312 |
|
|
|
| 313 |
|
|
.load_wr(load_wr),
|
| 314 |
|
|
|
| 315 |
|
|
.ch_load_wr(ch_load_wr),
|
| 316 |
|
|
|
| 317 |
|
|
//rd data
|
| 318 |
|
|
.ch_fifo_wr_num(ch_fifo_wr_num),
|
| 319 |
|
|
.rd_transfer_num(rd_transfer_num),
|
| 320 |
|
|
.rd_clr_line_num(rd_clr_line_num),
|
| 321 |
|
|
|
| 322 |
|
|
.rd_transfer(rd_transfer),
|
| 323 |
|
|
.rd_clr_line(rd_clr_line),
|
| 324 |
|
|
.fifo_wr(fifo_wr),
|
| 325 |
|
|
|
| 326 |
|
|
.ch_rd_clr_line(ch_rd_clr_line),
|
| 327 |
|
|
.ch_rd_transfer(ch_rd_transfer),
|
| 328 |
|
|
.ch_fifo_wr(ch_fifo_wr),
|
| 329 |
|
|
|
| 330 |
|
|
//rd resp
|
| 331 |
|
|
.rd_ch_num_resp(rd_ch_num_resp),
|
| 332 |
|
|
|
| 333 |
|
|
.rd_slverr(rd_slverr),
|
| 334 |
|
|
.rd_decerr(rd_decerr),
|
| 335 |
|
|
.rd_clr(rd_clr),
|
| 336 |
|
|
.rd_clr_load(rd_clr_load),
|
| 337 |
|
|
|
| 338 |
|
|
.ch_rd_slverr(ch_rd_slverr),
|
| 339 |
|
|
.ch_rd_decerr(ch_rd_decerr),
|
| 340 |
|
|
.ch_rd_clr(ch_rd_clr),
|
| 341 |
|
|
.ch_rd_clr_load(ch_rd_clr_load),
|
| 342 |
|
|
|
| 343 |
|
|
//wr cmd
|
| 344 |
|
|
.wr_ch_num(wr_ch_num),
|
| 345 |
|
|
.wr_cmd_num(wr_cmd_num),
|
| 346 |
|
|
|
| 347 |
|
|
.wr_last_cmd(wr_last_cmd),
|
| 348 |
|
|
.wr_line_cmd(wr_line_cmd),
|
| 349 |
|
|
.wr_go_next_line(wr_go_next_line),
|
| 350 |
|
|
.wr_burst_start(wr_burst_start),
|
| 351 |
|
|
.wr_burst_addr(wr_burst_addr),
|
| 352 |
|
|
.wr_burst_size(wr_burst_size),
|
| 353 |
|
|
.wr_tokens(wr_tokens),
|
| 354 |
|
|
.wr_cmd_port(wr_cmd_port),
|
| 355 |
|
|
.wr_periph_delay(wr_periph_delay),
|
| 356 |
|
|
.wr_clr_valid(wr_clr_valid),
|
| 357 |
|
|
.wr_cmd_split(wr_cmd_split),
|
| 358 |
|
|
.wr_clr_stall(wr_clr_stall),
|
| 359 |
|
|
|
| 360 |
|
|
.ch_wr_last_cmd(ch_wr_last_cmd),
|
| 361 |
|
|
.ch_wr_line_cmd(ch_wr_line_cmd),
|
| 362 |
|
|
.ch_wr_go_next_line(ch_wr_go_next_line),
|
| 363 |
|
|
.ch_wr_burst_start(ch_wr_burst_start),
|
| 364 |
|
|
.ch_wr_burst_addr(ch_wr_burst_addr),
|
| 365 |
|
|
.ch_wr_burst_size(ch_wr_burst_size),
|
| 366 |
|
|
.ch_wr_tokens(ch_wr_tokens),
|
| 367 |
|
|
.ch_wr_port_num(ch_wr_port_num),
|
| 368 |
|
|
.ch_wr_periph_delay(ch_wr_periph_delay),
|
| 369 |
|
|
.ch_wr_clr_valid(ch_wr_clr_valid),
|
| 370 |
|
|
.ch_wr_cmd_split(ch_wr_cmd_split),
|
| 371 |
|
|
.ch_wr_clr_stall(ch_wr_clr_stall),
|
| 372 |
|
|
|
| 373 |
|
|
//wr data
|
| 374 |
|
|
.ch_fifo_rd_num(ch_fifo_rd_num),
|
| 375 |
|
|
.wr_transfer_num(wr_transfer_num),
|
| 376 |
|
|
.wr_clr_line_num(wr_clr_line_num),
|
| 377 |
|
|
|
| 378 |
|
|
.wr_transfer(wr_transfer),
|
| 379 |
|
|
.wr_clr_line(wr_clr_line),
|
| 380 |
|
|
.fifo_rd(fifo_rd),
|
| 381 |
|
|
.fifo_wr_ready(fifo_wr_ready),
|
| 382 |
|
|
|
| 383 |
|
|
.ch_wr_transfer(ch_wr_transfer),
|
| 384 |
|
|
.ch_wr_clr_line(ch_wr_clr_line),
|
| 385 |
|
|
.ch_fifo_rd(ch_fifo_rd),
|
| 386 |
|
|
.ch_fifo_wr_ready(ch_fifo_wr_ready),
|
| 387 |
|
|
|
| 388 |
|
|
//wr resp
|
| 389 |
|
|
.wr_ch_num_resp(wr_ch_num_resp),
|
| 390 |
|
|
|
| 391 |
|
|
.wr_slverr(wr_slverr),
|
| 392 |
|
|
.wr_decerr(wr_decerr),
|
| 393 |
|
|
.wr_clr(wr_clr),
|
| 394 |
|
|
.wr_clr_last(wr_clr_last),
|
| 395 |
|
|
|
| 396 |
|
|
.ch_wr_slverr(ch_wr_slverr),
|
| 397 |
|
|
.ch_wr_decerr(ch_wr_decerr),
|
| 398 |
|
|
.ch_wr_clr_last(ch_wr_clr_last),
|
| 399 |
|
|
.ch_wr_clr(ch_wr_clr)
|
| 400 |
|
|
);
|
| 401 |
|
|
|
| 402 |
|
|
|
| 403 |
|
|
|
| 404 |
|
|
dma_ahb32_core0_ch dma_ahb32_core0_ch0 (
|
| 405 |
|
|
.clk(clk),
|
| 406 |
|
|
.reset(reset),
|
| 407 |
|
|
.scan_en(scan_en),
|
| 408 |
|
|
.idle(ch_idle[0]),
|
| 409 |
|
|
|
| 410 |
|
|
//APB
|
| 411 |
|
|
.pclk(pclk),
|
| 412 |
|
|
.clken(clken),
|
| 413 |
|
|
.pclken(pclken),
|
| 414 |
|
|
.psel(ch_psel[0]),
|
| 415 |
|
|
.penable(penable),
|
| 416 |
|
|
.paddr(paddr[7:0]),
|
| 417 |
|
|
.pwrite(pwrite),
|
| 418 |
|
|
.pwdata(pwdata),
|
| 419 |
|
|
.prdata(ch_prdata[31+32*0:32*0]),
|
| 420 |
|
|
.pslverr(ch_pslverr[0]),
|
| 421 |
|
|
|
| 422 |
|
|
//PERIPH
|
| 423 |
|
|
.periph_tx_req(periph_tx_req),
|
| 424 |
|
|
.periph_tx_clr(ch_periph_tx_clr[31*0+31-1:31*0]),
|
| 425 |
|
|
.periph_rx_req(periph_rx_req),
|
| 426 |
|
|
.periph_rx_clr(ch_periph_rx_clr[31*0+31-1:31*0]),
|
| 427 |
|
|
|
| 428 |
|
|
//RD AXIM
|
| 429 |
|
|
.rd_cmd_split(ch_rd_cmd_split[0]),
|
| 430 |
|
|
.rd_cmd_line(ch_rd_cmd_line[0]),
|
| 431 |
|
|
.rd_clr_line(ch_rd_clr_line[0]),
|
| 432 |
|
|
.rd_clr(ch_rd_clr[0]),
|
| 433 |
|
|
.rd_clr_load(ch_rd_clr_load[0]),
|
| 434 |
|
|
.rd_slverr(ch_rd_slverr[0]),
|
| 435 |
|
|
.rd_decerr(ch_rd_decerr[0]),
|
| 436 |
|
|
.rd_line_cmd(ch_rd_line_cmd[0]),
|
| 437 |
|
|
.rd_go_next_line(ch_rd_go_next_line[0]),
|
| 438 |
|
|
.rd_transfer(ch_rd_transfer[0]),
|
| 439 |
|
|
.rd_transfer_size(rd_transfer_size),
|
| 440 |
|
|
.rd_clr_stall(ch_rd_clr_stall[0]),
|
| 441 |
|
|
|
| 442 |
|
|
//WR AXIM
|
| 443 |
|
|
.wr_cmd_split(ch_wr_cmd_split[0]),
|
| 444 |
|
|
.wr_cmd_pending(ch_wr_cmd_pending[0]),
|
| 445 |
|
|
.wr_clr_line(ch_wr_clr_line[0]),
|
| 446 |
|
|
.wr_clr(ch_wr_clr[0]),
|
| 447 |
|
|
.wr_clr_last(ch_wr_clr_last[0]),
|
| 448 |
|
|
.wr_slverr(ch_wr_slverr[0]),
|
| 449 |
|
|
.wr_decerr(ch_wr_decerr[0]),
|
| 450 |
|
|
.wr_last_cmd(ch_wr_last_cmd[0]),
|
| 451 |
|
|
.wr_line_cmd(ch_wr_line_cmd[0]),
|
| 452 |
|
|
.wr_go_next_line(ch_wr_go_next_line[0]),
|
| 453 |
|
|
.wr_transfer(ch_wr_transfer[0]),
|
| 454 |
|
|
.wr_transfer_size(wr_transfer_size),
|
| 455 |
|
|
.wr_next_size(wr_next_size),
|
| 456 |
|
|
.wr_clr_stall(ch_wr_clr_stall[0]),
|
| 457 |
|
|
|
| 458 |
|
|
.timeout_aw(ch_timeout_aw[0]),
|
| 459 |
|
|
.timeout_w(ch_timeout_w[0]),
|
| 460 |
|
|
.timeout_ar(ch_timeout_ar[0]),
|
| 461 |
|
|
.wdt_timeout(ch_wdt_timeout[0]),
|
| 462 |
|
|
|
| 463 |
|
|
//LOAD CMD
|
| 464 |
|
|
.load_wr(ch_load_wr[0]),
|
| 465 |
|
|
.load_wr_cycle(load_wr_cycle),
|
| 466 |
|
|
.load_wdata(load_wdata),
|
| 467 |
|
|
.load_req_in_prog(ch_load_req_in_prog[0]),
|
| 468 |
|
|
|
| 469 |
|
|
//CTRL
|
| 470 |
|
|
.ch_active(ch_active[0]),
|
| 471 |
|
|
.ch_rd_active(ch_rd_active[0]),
|
| 472 |
|
|
.ch_wr_active(ch_wr_active[0]),
|
| 473 |
|
|
|
| 474 |
|
|
//RD CTRL
|
| 475 |
|
|
.rd_burst_start(ch_rd_burst_start[0]),
|
| 476 |
|
|
.rd_ready(ch_rd_ready[0]),
|
| 477 |
|
|
.rd_burst_addr(ch_rd_burst_addr[32-1+32*0:32*0]),
|
| 478 |
|
|
.rd_burst_size(ch_rd_burst_size[7-1+7*0:7*0]),
|
| 479 |
|
|
.rd_tokens(ch_rd_tokens[`TOKEN_BITS-1+`TOKEN_BITS*0:`TOKEN_BITS*0]),
|
| 480 |
|
|
.rd_port_num(ch_rd_port_num[0]),
|
| 481 |
|
|
.rd_periph_delay(ch_rd_periph_delay[`DELAY_BITS-1+`DELAY_BITS*0:`DELAY_BITS*0]),
|
| 482 |
|
|
.rd_clr_valid(ch_rd_clr_valid[0]),
|
| 483 |
|
|
|
| 484 |
|
|
//WR CTRL
|
| 485 |
|
|
.wr_burst_start(ch_wr_burst_start[0]),
|
| 486 |
|
|
.wr_ready(ch_wr_ready[0]),
|
| 487 |
|
|
.wr_burst_addr(ch_wr_burst_addr[32-1+32*0:32*0]),
|
| 488 |
|
|
.wr_burst_size(ch_wr_burst_size[7-1+7*0:7*0]),
|
| 489 |
|
|
.wr_tokens(ch_wr_tokens[`TOKEN_BITS-1+`TOKEN_BITS*0:`TOKEN_BITS*0]),
|
| 490 |
|
|
.wr_port_num(ch_wr_port_num[0]),
|
| 491 |
|
|
.wr_periph_delay(ch_wr_periph_delay[`DELAY_BITS-1+`DELAY_BITS*0:`DELAY_BITS*0]),
|
| 492 |
|
|
.wr_clr_valid(ch_wr_clr_valid[0]),
|
| 493 |
|
|
|
| 494 |
|
|
//FIFO
|
| 495 |
|
|
.fifo_wr(ch_fifo_wr[0]),
|
| 496 |
|
|
.fifo_wdata(fifo_wdata),
|
| 497 |
|
|
.fifo_wsize(fifo_wsize),
|
| 498 |
|
|
.fifo_rd(ch_fifo_rd[0]),
|
| 499 |
|
|
.fifo_rsize(fifo_rsize),
|
| 500 |
|
|
.fifo_rd_valid(ch_fifo_rd_valid[0]),
|
| 501 |
|
|
.fifo_rdata(ch_fifo_rdata[(32-1)+32*0:32*0]),
|
| 502 |
|
|
.fifo_wr_ready(ch_fifo_wr_ready[0]),
|
| 503 |
|
|
|
| 504 |
|
|
.joint_mode(joint_mode),
|
| 505 |
|
|
.joint_remote(joint_remote),
|
| 506 |
|
|
.rd_page_cross(ch_rd_page_cross[0]),
|
| 507 |
|
|
.wr_page_cross(ch_wr_page_cross[0]),
|
| 508 |
|
|
.joint_in_prog(ch_joint_in_prog[0]),
|
| 509 |
|
|
.joint_not_in_prog(ch_joint_not_in_prog[0]),
|
| 510 |
|
|
.joint_mux_in_prog(ch_joint_mux_in_prog[0]),
|
| 511 |
|
|
.joint_req(ch_joint_req[0]),
|
| 512 |
|
|
|
| 513 |
|
|
.ch_start(ch_start[0]),
|
| 514 |
|
|
|
| 515 |
|
|
//INT
|
| 516 |
|
|
.int_all_proc(ch_int_all_proc[1-1+(1*0):1*0])
|
| 517 |
|
|
);
|
| 518 |
|
|
|
| 519 |
|
|
dma_ahb32_core0_ch_empty dma_ahb32_core0_ch_empty1 (
|
| 520 |
|
|
.clk(clk),
|
| 521 |
|
|
.reset(reset),
|
| 522 |
|
|
.scan_en(scan_en),
|
| 523 |
|
|
.idle(ch_idle[1]),
|
| 524 |
|
|
|
| 525 |
|
|
//APB
|
| 526 |
|
|
.pclk(pclk),
|
| 527 |
|
|
.clken(clken),
|
| 528 |
|
|
.pclken(pclken),
|
| 529 |
|
|
.psel(ch_psel[1]),
|
| 530 |
|
|
.penable(penable),
|
| 531 |
|
|
.paddr(paddr[7:0]),
|
| 532 |
|
|
.pwrite(pwrite),
|
| 533 |
|
|
.pwdata(pwdata),
|
| 534 |
|
|
.prdata(ch_prdata[31+32*1:32*1]),
|
| 535 |
|
|
.pslverr(ch_pslverr[1]),
|
| 536 |
|
|
|
| 537 |
|
|
//PERIPH
|
| 538 |
|
|
.periph_tx_req(periph_tx_req),
|
| 539 |
|
|
.periph_tx_clr(ch_periph_tx_clr[31*1+31-1:31*1]),
|
| 540 |
|
|
.periph_rx_req(periph_rx_req),
|
| 541 |
|
|
.periph_rx_clr(ch_periph_rx_clr[31*1+31-1:31*1]),
|
| 542 |
|
|
|
| 543 |
|
|
//RD AXIM
|
| 544 |
|
|
.rd_cmd_split(ch_rd_cmd_split[1]),
|
| 545 |
|
|
.rd_cmd_line(ch_rd_cmd_line[1]),
|
| 546 |
|
|
.rd_clr_line(ch_rd_clr_line[1]),
|
| 547 |
|
|
.rd_clr(ch_rd_clr[1]),
|
| 548 |
|
|
.rd_clr_load(ch_rd_clr_load[1]),
|
| 549 |
|
|
.rd_slverr(ch_rd_slverr[1]),
|
| 550 |
|
|
.rd_decerr(ch_rd_decerr[1]),
|
| 551 |
|
|
.rd_line_cmd(ch_rd_line_cmd[1]),
|
| 552 |
|
|
.rd_go_next_line(ch_rd_go_next_line[1]),
|
| 553 |
|
|
.rd_transfer(ch_rd_transfer[1]),
|
| 554 |
|
|
.rd_transfer_size(rd_transfer_size),
|
| 555 |
|
|
.rd_clr_stall(ch_rd_clr_stall[1]),
|
| 556 |
|
|
|
| 557 |
|
|
//WR AXIM
|
| 558 |
|
|
.wr_cmd_split(ch_wr_cmd_split[1]),
|
| 559 |
|
|
.wr_cmd_pending(ch_wr_cmd_pending[1]),
|
| 560 |
|
|
.wr_clr_line(ch_wr_clr_line[1]),
|
| 561 |
|
|
.wr_clr(ch_wr_clr[1]),
|
| 562 |
|
|
.wr_clr_last(ch_wr_clr_last[1]),
|
| 563 |
|
|
.wr_slverr(ch_wr_slverr[1]),
|
| 564 |
|
|
.wr_decerr(ch_wr_decerr[1]),
|
| 565 |
|
|
.wr_last_cmd(ch_wr_last_cmd[1]),
|
| 566 |
|
|
.wr_line_cmd(ch_wr_line_cmd[1]),
|
| 567 |
|
|
.wr_go_next_line(ch_wr_go_next_line[1]),
|
| 568 |
|
|
.wr_transfer(ch_wr_transfer[1]),
|
| 569 |
|
|
.wr_transfer_size(wr_transfer_size),
|
| 570 |
|
|
.wr_next_size(wr_next_size),
|
| 571 |
|
|
.wr_clr_stall(ch_wr_clr_stall[1]),
|
| 572 |
|
|
|
| 573 |
|
|
.timeout_aw(ch_timeout_aw[1]),
|
| 574 |
|
|
.timeout_w(ch_timeout_w[1]),
|
| 575 |
|
|
.timeout_ar(ch_timeout_ar[1]),
|
| 576 |
|
|
.wdt_timeout(ch_wdt_timeout[1]),
|
| 577 |
|
|
|
| 578 |
|
|
//LOAD CMD
|
| 579 |
|
|
.load_wr(ch_load_wr[1]),
|
| 580 |
|
|
.load_wr_cycle(load_wr_cycle),
|
| 581 |
|
|
.load_wdata(load_wdata),
|
| 582 |
|
|
.load_req_in_prog(ch_load_req_in_prog[1]),
|
| 583 |
|
|
|
| 584 |
|
|
//CTRL
|
| 585 |
|
|
.ch_active(ch_active[1]),
|
| 586 |
|
|
.ch_rd_active(ch_rd_active[1]),
|
| 587 |
|
|
.ch_wr_active(ch_wr_active[1]),
|
| 588 |
|
|
|
| 589 |
|
|
//RD CTRL
|
| 590 |
|
|
.rd_burst_start(ch_rd_burst_start[1]),
|
| 591 |
|
|
.rd_ready(ch_rd_ready[1]),
|
| 592 |
|
|
.rd_burst_addr(ch_rd_burst_addr[32-1+32*1:32*1]),
|
| 593 |
|
|
.rd_burst_size(ch_rd_burst_size[7-1+7*1:7*1]),
|
| 594 |
|
|
.rd_tokens(ch_rd_tokens[`TOKEN_BITS-1+`TOKEN_BITS*1:`TOKEN_BITS*1]),
|
| 595 |
|
|
.rd_port_num(ch_rd_port_num[1]),
|
| 596 |
|
|
.rd_periph_delay(ch_rd_periph_delay[`DELAY_BITS-1+`DELAY_BITS*1:`DELAY_BITS*1]),
|
| 597 |
|
|
.rd_clr_valid(ch_rd_clr_valid[1]),
|
| 598 |
|
|
|
| 599 |
|
|
//WR CTRL
|
| 600 |
|
|
.wr_burst_start(ch_wr_burst_start[1]),
|
| 601 |
|
|
.wr_ready(ch_wr_ready[1]),
|
| 602 |
|
|
.wr_burst_addr(ch_wr_burst_addr[32-1+32*1:32*1]),
|
| 603 |
|
|
.wr_burst_size(ch_wr_burst_size[7-1+7*1:7*1]),
|
| 604 |
|
|
.wr_tokens(ch_wr_tokens[`TOKEN_BITS-1+`TOKEN_BITS*1:`TOKEN_BITS*1]),
|
| 605 |
|
|
.wr_port_num(ch_wr_port_num[1]),
|
| 606 |
|
|
.wr_periph_delay(ch_wr_periph_delay[`DELAY_BITS-1+`DELAY_BITS*1:`DELAY_BITS*1]),
|
| 607 |
|
|
.wr_clr_valid(ch_wr_clr_valid[1]),
|
| 608 |
|
|
|
| 609 |
|
|
//FIFO
|
| 610 |
|
|
.fifo_wr(ch_fifo_wr[1]),
|
| 611 |
|
|
.fifo_wdata(fifo_wdata),
|
| 612 |
|
|
.fifo_wsize(fifo_wsize),
|
| 613 |
|
|
.fifo_rd(ch_fifo_rd[1]),
|
| 614 |
|
|
.fifo_rsize(fifo_rsize),
|
| 615 |
|
|
.fifo_rd_valid(ch_fifo_rd_valid[1]),
|
| 616 |
|
|
.fifo_rdata(ch_fifo_rdata[(32-1)+32*1:32*1]),
|
| 617 |
|
|
.fifo_wr_ready(ch_fifo_wr_ready[1]),
|
| 618 |
|
|
|
| 619 |
|
|
.joint_mode(joint_mode),
|
| 620 |
|
|
.joint_remote(joint_remote),
|
| 621 |
|
|
.rd_page_cross(ch_rd_page_cross[1]),
|
| 622 |
|
|
.wr_page_cross(ch_wr_page_cross[1]),
|
| 623 |
|
|
.joint_in_prog(ch_joint_in_prog[1]),
|
| 624 |
|
|
.joint_not_in_prog(ch_joint_not_in_prog[1]),
|
| 625 |
|
|
.joint_mux_in_prog(ch_joint_mux_in_prog[1]),
|
| 626 |
|
|
.joint_req(ch_joint_req[1]),
|
| 627 |
|
|
|
| 628 |
|
|
.ch_start(ch_start[1]),
|
| 629 |
|
|
|
| 630 |
|
|
//INT
|
| 631 |
|
|
.int_all_proc(ch_int_all_proc[1-1+(1*1):1*1])
|
| 632 |
|
|
);
|
| 633 |
|
|
|
| 634 |
|
|
dma_ahb32_core0_ch_empty dma_ahb32_core0_ch_empty2 (
|
| 635 |
|
|
.clk(clk),
|
| 636 |
|
|
.reset(reset),
|
| 637 |
|
|
.scan_en(scan_en),
|
| 638 |
|
|
.idle(ch_idle[2]),
|
| 639 |
|
|
|
| 640 |
|
|
//APB
|
| 641 |
|
|
.pclk(pclk),
|
| 642 |
|
|
.clken(clken),
|
| 643 |
|
|
.pclken(pclken),
|
| 644 |
|
|
.psel(ch_psel[2]),
|
| 645 |
|
|
.penable(penable),
|
| 646 |
|
|
.paddr(paddr[7:0]),
|
| 647 |
|
|
.pwrite(pwrite),
|
| 648 |
|
|
.pwdata(pwdata),
|
| 649 |
|
|
.prdata(ch_prdata[31+32*2:32*2]),
|
| 650 |
|
|
.pslverr(ch_pslverr[2]),
|
| 651 |
|
|
|
| 652 |
|
|
//PERIPH
|
| 653 |
|
|
.periph_tx_req(periph_tx_req),
|
| 654 |
|
|
.periph_tx_clr(ch_periph_tx_clr[31*2+31-1:31*2]),
|
| 655 |
|
|
.periph_rx_req(periph_rx_req),
|
| 656 |
|
|
.periph_rx_clr(ch_periph_rx_clr[31*2+31-1:31*2]),
|
| 657 |
|
|
|
| 658 |
|
|
//RD AXIM
|
| 659 |
|
|
.rd_cmd_split(ch_rd_cmd_split[2]),
|
| 660 |
|
|
.rd_cmd_line(ch_rd_cmd_line[2]),
|
| 661 |
|
|
.rd_clr_line(ch_rd_clr_line[2]),
|
| 662 |
|
|
.rd_clr(ch_rd_clr[2]),
|
| 663 |
|
|
.rd_clr_load(ch_rd_clr_load[2]),
|
| 664 |
|
|
.rd_slverr(ch_rd_slverr[2]),
|
| 665 |
|
|
.rd_decerr(ch_rd_decerr[2]),
|
| 666 |
|
|
.rd_line_cmd(ch_rd_line_cmd[2]),
|
| 667 |
|
|
.rd_go_next_line(ch_rd_go_next_line[2]),
|
| 668 |
|
|
.rd_transfer(ch_rd_transfer[2]),
|
| 669 |
|
|
.rd_transfer_size(rd_transfer_size),
|
| 670 |
|
|
.rd_clr_stall(ch_rd_clr_stall[2]),
|
| 671 |
|
|
|
| 672 |
|
|
//WR AXIM
|
| 673 |
|
|
.wr_cmd_split(ch_wr_cmd_split[2]),
|
| 674 |
|
|
.wr_cmd_pending(ch_wr_cmd_pending[2]),
|
| 675 |
|
|
.wr_clr_line(ch_wr_clr_line[2]),
|
| 676 |
|
|
.wr_clr(ch_wr_clr[2]),
|
| 677 |
|
|
.wr_clr_last(ch_wr_clr_last[2]),
|
| 678 |
|
|
.wr_slverr(ch_wr_slverr[2]),
|
| 679 |
|
|
.wr_decerr(ch_wr_decerr[2]),
|
| 680 |
|
|
.wr_last_cmd(ch_wr_last_cmd[2]),
|
| 681 |
|
|
.wr_line_cmd(ch_wr_line_cmd[2]),
|
| 682 |
|
|
.wr_go_next_line(ch_wr_go_next_line[2]),
|
| 683 |
|
|
.wr_transfer(ch_wr_transfer[2]),
|
| 684 |
|
|
.wr_transfer_size(wr_transfer_size),
|
| 685 |
|
|
.wr_next_size(wr_next_size),
|
| 686 |
|
|
.wr_clr_stall(ch_wr_clr_stall[2]),
|
| 687 |
|
|
|
| 688 |
|
|
.timeout_aw(ch_timeout_aw[2]),
|
| 689 |
|
|
.timeout_w(ch_timeout_w[2]),
|
| 690 |
|
|
.timeout_ar(ch_timeout_ar[2]),
|
| 691 |
|
|
.wdt_timeout(ch_wdt_timeout[2]),
|
| 692 |
|
|
|
| 693 |
|
|
//LOAD CMD
|
| 694 |
|
|
.load_wr(ch_load_wr[2]),
|
| 695 |
|
|
.load_wr_cycle(load_wr_cycle),
|
| 696 |
|
|
.load_wdata(load_wdata),
|
| 697 |
|
|
.load_req_in_prog(ch_load_req_in_prog[2]),
|
| 698 |
|
|
|
| 699 |
|
|
//CTRL
|
| 700 |
|
|
.ch_active(ch_active[2]),
|
| 701 |
|
|
.ch_rd_active(ch_rd_active[2]),
|
| 702 |
|
|
.ch_wr_active(ch_wr_active[2]),
|
| 703 |
|
|
|
| 704 |
|
|
//RD CTRL
|
| 705 |
|
|
.rd_burst_start(ch_rd_burst_start[2]),
|
| 706 |
|
|
.rd_ready(ch_rd_ready[2]),
|
| 707 |
|
|
.rd_burst_addr(ch_rd_burst_addr[32-1+32*2:32*2]),
|
| 708 |
|
|
.rd_burst_size(ch_rd_burst_size[7-1+7*2:7*2]),
|
| 709 |
|
|
.rd_tokens(ch_rd_tokens[`TOKEN_BITS-1+`TOKEN_BITS*2:`TOKEN_BITS*2]),
|
| 710 |
|
|
.rd_port_num(ch_rd_port_num[2]),
|
| 711 |
|
|
.rd_periph_delay(ch_rd_periph_delay[`DELAY_BITS-1+`DELAY_BITS*2:`DELAY_BITS*2]),
|
| 712 |
|
|
.rd_clr_valid(ch_rd_clr_valid[2]),
|
| 713 |
|
|
|
| 714 |
|
|
//WR CTRL
|
| 715 |
|
|
.wr_burst_start(ch_wr_burst_start[2]),
|
| 716 |
|
|
.wr_ready(ch_wr_ready[2]),
|
| 717 |
|
|
.wr_burst_addr(ch_wr_burst_addr[32-1+32*2:32*2]),
|
| 718 |
|
|
.wr_burst_size(ch_wr_burst_size[7-1+7*2:7*2]),
|
| 719 |
|
|
.wr_tokens(ch_wr_tokens[`TOKEN_BITS-1+`TOKEN_BITS*2:`TOKEN_BITS*2]),
|
| 720 |
|
|
.wr_port_num(ch_wr_port_num[2]),
|
| 721 |
|
|
.wr_periph_delay(ch_wr_periph_delay[`DELAY_BITS-1+`DELAY_BITS*2:`DELAY_BITS*2]),
|
| 722 |
|
|
.wr_clr_valid(ch_wr_clr_valid[2]),
|
| 723 |
|
|
|
| 724 |
|
|
//FIFO
|
| 725 |
|
|
.fifo_wr(ch_fifo_wr[2]),
|
| 726 |
|
|
.fifo_wdata(fifo_wdata),
|
| 727 |
|
|
.fifo_wsize(fifo_wsize),
|
| 728 |
|
|
.fifo_rd(ch_fifo_rd[2]),
|
| 729 |
|
|
.fifo_rsize(fifo_rsize),
|
| 730 |
|
|
.fifo_rd_valid(ch_fifo_rd_valid[2]),
|
| 731 |
|
|
.fifo_rdata(ch_fifo_rdata[(32-1)+32*2:32*2]),
|
| 732 |
|
|
.fifo_wr_ready(ch_fifo_wr_ready[2]),
|
| 733 |
|
|
|
| 734 |
|
|
.joint_mode(joint_mode),
|
| 735 |
|
|
.joint_remote(joint_remote),
|
| 736 |
|
|
.rd_page_cross(ch_rd_page_cross[2]),
|
| 737 |
|
|
.wr_page_cross(ch_wr_page_cross[2]),
|
| 738 |
|
|
.joint_in_prog(ch_joint_in_prog[2]),
|
| 739 |
|
|
.joint_not_in_prog(ch_joint_not_in_prog[2]),
|
| 740 |
|
|
.joint_mux_in_prog(ch_joint_mux_in_prog[2]),
|
| 741 |
|
|
.joint_req(ch_joint_req[2]),
|
| 742 |
|
|
|
| 743 |
|
|
.ch_start(ch_start[2]),
|
| 744 |
|
|
|
| 745 |
|
|
//INT
|
| 746 |
|
|
.int_all_proc(ch_int_all_proc[1-1+(1*2):1*2])
|
| 747 |
|
|
);
|
| 748 |
|
|
|
| 749 |
|
|
dma_ahb32_core0_ch_empty dma_ahb32_core0_ch_empty3 (
|
| 750 |
|
|
.clk(clk),
|
| 751 |
|
|
.reset(reset),
|
| 752 |
|
|
.scan_en(scan_en),
|
| 753 |
|
|
.idle(ch_idle[3]),
|
| 754 |
|
|
|
| 755 |
|
|
//APB
|
| 756 |
|
|
.pclk(pclk),
|
| 757 |
|
|
.clken(clken),
|
| 758 |
|
|
.pclken(pclken),
|
| 759 |
|
|
.psel(ch_psel[3]),
|
| 760 |
|
|
.penable(penable),
|
| 761 |
|
|
.paddr(paddr[7:0]),
|
| 762 |
|
|
.pwrite(pwrite),
|
| 763 |
|
|
.pwdata(pwdata),
|
| 764 |
|
|
.prdata(ch_prdata[31+32*3:32*3]),
|
| 765 |
|
|
.pslverr(ch_pslverr[3]),
|
| 766 |
|
|
|
| 767 |
|
|
//PERIPH
|
| 768 |
|
|
.periph_tx_req(periph_tx_req),
|
| 769 |
|
|
.periph_tx_clr(ch_periph_tx_clr[31*3+31-1:31*3]),
|
| 770 |
|
|
.periph_rx_req(periph_rx_req),
|
| 771 |
|
|
.periph_rx_clr(ch_periph_rx_clr[31*3+31-1:31*3]),
|
| 772 |
|
|
|
| 773 |
|
|
//RD AXIM
|
| 774 |
|
|
.rd_cmd_split(ch_rd_cmd_split[3]),
|
| 775 |
|
|
.rd_cmd_line(ch_rd_cmd_line[3]),
|
| 776 |
|
|
.rd_clr_line(ch_rd_clr_line[3]),
|
| 777 |
|
|
.rd_clr(ch_rd_clr[3]),
|
| 778 |
|
|
.rd_clr_load(ch_rd_clr_load[3]),
|
| 779 |
|
|
.rd_slverr(ch_rd_slverr[3]),
|
| 780 |
|
|
.rd_decerr(ch_rd_decerr[3]),
|
| 781 |
|
|
.rd_line_cmd(ch_rd_line_cmd[3]),
|
| 782 |
|
|
.rd_go_next_line(ch_rd_go_next_line[3]),
|
| 783 |
|
|
.rd_transfer(ch_rd_transfer[3]),
|
| 784 |
|
|
.rd_transfer_size(rd_transfer_size),
|
| 785 |
|
|
.rd_clr_stall(ch_rd_clr_stall[3]),
|
| 786 |
|
|
|
| 787 |
|
|
//WR AXIM
|
| 788 |
|
|
.wr_cmd_split(ch_wr_cmd_split[3]),
|
| 789 |
|
|
.wr_cmd_pending(ch_wr_cmd_pending[3]),
|
| 790 |
|
|
.wr_clr_line(ch_wr_clr_line[3]),
|
| 791 |
|
|
.wr_clr(ch_wr_clr[3]),
|
| 792 |
|
|
.wr_clr_last(ch_wr_clr_last[3]),
|
| 793 |
|
|
.wr_slverr(ch_wr_slverr[3]),
|
| 794 |
|
|
.wr_decerr(ch_wr_decerr[3]),
|
| 795 |
|
|
.wr_last_cmd(ch_wr_last_cmd[3]),
|
| 796 |
|
|
.wr_line_cmd(ch_wr_line_cmd[3]),
|
| 797 |
|
|
.wr_go_next_line(ch_wr_go_next_line[3]),
|
| 798 |
|
|
.wr_transfer(ch_wr_transfer[3]),
|
| 799 |
|
|
.wr_transfer_size(wr_transfer_size),
|
| 800 |
|
|
.wr_next_size(wr_next_size),
|
| 801 |
|
|
.wr_clr_stall(ch_wr_clr_stall[3]),
|
| 802 |
|
|
|
| 803 |
|
|
.timeout_aw(ch_timeout_aw[3]),
|
| 804 |
|
|
.timeout_w(ch_timeout_w[3]),
|
| 805 |
|
|
.timeout_ar(ch_timeout_ar[3]),
|
| 806 |
|
|
.wdt_timeout(ch_wdt_timeout[3]),
|
| 807 |
|
|
|
| 808 |
|
|
//LOAD CMD
|
| 809 |
|
|
.load_wr(ch_load_wr[3]),
|
| 810 |
|
|
.load_wr_cycle(load_wr_cycle),
|
| 811 |
|
|
.load_wdata(load_wdata),
|
| 812 |
|
|
.load_req_in_prog(ch_load_req_in_prog[3]),
|
| 813 |
|
|
|
| 814 |
|
|
//CTRL
|
| 815 |
|
|
.ch_active(ch_active[3]),
|
| 816 |
|
|
.ch_rd_active(ch_rd_active[3]),
|
| 817 |
|
|
.ch_wr_active(ch_wr_active[3]),
|
| 818 |
|
|
|
| 819 |
|
|
//RD CTRL
|
| 820 |
|
|
.rd_burst_start(ch_rd_burst_start[3]),
|
| 821 |
|
|
.rd_ready(ch_rd_ready[3]),
|
| 822 |
|
|
.rd_burst_addr(ch_rd_burst_addr[32-1+32*3:32*3]),
|
| 823 |
|
|
.rd_burst_size(ch_rd_burst_size[7-1+7*3:7*3]),
|
| 824 |
|
|
.rd_tokens(ch_rd_tokens[`TOKEN_BITS-1+`TOKEN_BITS*3:`TOKEN_BITS*3]),
|
| 825 |
|
|
.rd_port_num(ch_rd_port_num[3]),
|
| 826 |
|
|
.rd_periph_delay(ch_rd_periph_delay[`DELAY_BITS-1+`DELAY_BITS*3:`DELAY_BITS*3]),
|
| 827 |
|
|
.rd_clr_valid(ch_rd_clr_valid[3]),
|
| 828 |
|
|
|
| 829 |
|
|
//WR CTRL
|
| 830 |
|
|
.wr_burst_start(ch_wr_burst_start[3]),
|
| 831 |
|
|
.wr_ready(ch_wr_ready[3]),
|
| 832 |
|
|
.wr_burst_addr(ch_wr_burst_addr[32-1+32*3:32*3]),
|
| 833 |
|
|
.wr_burst_size(ch_wr_burst_size[7-1+7*3:7*3]),
|
| 834 |
|
|
.wr_tokens(ch_wr_tokens[`TOKEN_BITS-1+`TOKEN_BITS*3:`TOKEN_BITS*3]),
|
| 835 |
|
|
.wr_port_num(ch_wr_port_num[3]),
|
| 836 |
|
|
.wr_periph_delay(ch_wr_periph_delay[`DELAY_BITS-1+`DELAY_BITS*3:`DELAY_BITS*3]),
|
| 837 |
|
|
.wr_clr_valid(ch_wr_clr_valid[3]),
|
| 838 |
|
|
|
| 839 |
|
|
//FIFO
|
| 840 |
|
|
.fifo_wr(ch_fifo_wr[3]),
|
| 841 |
|
|
.fifo_wdata(fifo_wdata),
|
| 842 |
|
|
.fifo_wsize(fifo_wsize),
|
| 843 |
|
|
.fifo_rd(ch_fifo_rd[3]),
|
| 844 |
|
|
.fifo_rsize(fifo_rsize),
|
| 845 |
|
|
.fifo_rd_valid(ch_fifo_rd_valid[3]),
|
| 846 |
|
|
.fifo_rdata(ch_fifo_rdata[(32-1)+32*3:32*3]),
|
| 847 |
|
|
.fifo_wr_ready(ch_fifo_wr_ready[3]),
|
| 848 |
|
|
|
| 849 |
|
|
.joint_mode(joint_mode),
|
| 850 |
|
|
.joint_remote(joint_remote),
|
| 851 |
|
|
.rd_page_cross(ch_rd_page_cross[3]),
|
| 852 |
|
|
.wr_page_cross(ch_wr_page_cross[3]),
|
| 853 |
|
|
.joint_in_prog(ch_joint_in_prog[3]),
|
| 854 |
|
|
.joint_not_in_prog(ch_joint_not_in_prog[3]),
|
| 855 |
|
|
.joint_mux_in_prog(ch_joint_mux_in_prog[3]),
|
| 856 |
|
|
.joint_req(ch_joint_req[3]),
|
| 857 |
|
|
|
| 858 |
|
|
.ch_start(ch_start[3]),
|
| 859 |
|
|
|
| 860 |
|
|
//INT
|
| 861 |
|
|
.int_all_proc(ch_int_all_proc[1-1+(1*3):1*3])
|
| 862 |
|
|
);
|
| 863 |
|
|
|
| 864 |
|
|
dma_ahb32_core0_ch_empty dma_ahb32_core0_ch_empty4 (
|
| 865 |
|
|
.clk(clk),
|
| 866 |
|
|
.reset(reset),
|
| 867 |
|
|
.scan_en(scan_en),
|
| 868 |
|
|
.idle(ch_idle[4]),
|
| 869 |
|
|
|
| 870 |
|
|
//APB
|
| 871 |
|
|
.pclk(pclk),
|
| 872 |
|
|
.clken(clken),
|
| 873 |
|
|
.pclken(pclken),
|
| 874 |
|
|
.psel(ch_psel[4]),
|
| 875 |
|
|
.penable(penable),
|
| 876 |
|
|
.paddr(paddr[7:0]),
|
| 877 |
|
|
.pwrite(pwrite),
|
| 878 |
|
|
.pwdata(pwdata),
|
| 879 |
|
|
.prdata(ch_prdata[31+32*4:32*4]),
|
| 880 |
|
|
.pslverr(ch_pslverr[4]),
|
| 881 |
|
|
|
| 882 |
|
|
//PERIPH
|
| 883 |
|
|
.periph_tx_req(periph_tx_req),
|
| 884 |
|
|
.periph_tx_clr(ch_periph_tx_clr[31*4+31-1:31*4]),
|
| 885 |
|
|
.periph_rx_req(periph_rx_req),
|
| 886 |
|
|
.periph_rx_clr(ch_periph_rx_clr[31*4+31-1:31*4]),
|
| 887 |
|
|
|
| 888 |
|
|
//RD AXIM
|
| 889 |
|
|
.rd_cmd_split(ch_rd_cmd_split[4]),
|
| 890 |
|
|
.rd_cmd_line(ch_rd_cmd_line[4]),
|
| 891 |
|
|
.rd_clr_line(ch_rd_clr_line[4]),
|
| 892 |
|
|
.rd_clr(ch_rd_clr[4]),
|
| 893 |
|
|
.rd_clr_load(ch_rd_clr_load[4]),
|
| 894 |
|
|
.rd_slverr(ch_rd_slverr[4]),
|
| 895 |
|
|
.rd_decerr(ch_rd_decerr[4]),
|
| 896 |
|
|
.rd_line_cmd(ch_rd_line_cmd[4]),
|
| 897 |
|
|
.rd_go_next_line(ch_rd_go_next_line[4]),
|
| 898 |
|
|
.rd_transfer(ch_rd_transfer[4]),
|
| 899 |
|
|
.rd_transfer_size(rd_transfer_size),
|
| 900 |
|
|
.rd_clr_stall(ch_rd_clr_stall[4]),
|
| 901 |
|
|
|
| 902 |
|
|
//WR AXIM
|
| 903 |
|
|
.wr_cmd_split(ch_wr_cmd_split[4]),
|
| 904 |
|
|
.wr_cmd_pending(ch_wr_cmd_pending[4]),
|
| 905 |
|
|
.wr_clr_line(ch_wr_clr_line[4]),
|
| 906 |
|
|
.wr_clr(ch_wr_clr[4]),
|
| 907 |
|
|
.wr_clr_last(ch_wr_clr_last[4]),
|
| 908 |
|
|
.wr_slverr(ch_wr_slverr[4]),
|
| 909 |
|
|
.wr_decerr(ch_wr_decerr[4]),
|
| 910 |
|
|
.wr_last_cmd(ch_wr_last_cmd[4]),
|
| 911 |
|
|
.wr_line_cmd(ch_wr_line_cmd[4]),
|
| 912 |
|
|
.wr_go_next_line(ch_wr_go_next_line[4]),
|
| 913 |
|
|
.wr_transfer(ch_wr_transfer[4]),
|
| 914 |
|
|
.wr_transfer_size(wr_transfer_size),
|
| 915 |
|
|
.wr_next_size(wr_next_size),
|
| 916 |
|
|
.wr_clr_stall(ch_wr_clr_stall[4]),
|
| 917 |
|
|
|
| 918 |
|
|
.timeout_aw(ch_timeout_aw[4]),
|
| 919 |
|
|
.timeout_w(ch_timeout_w[4]),
|
| 920 |
|
|
.timeout_ar(ch_timeout_ar[4]),
|
| 921 |
|
|
.wdt_timeout(ch_wdt_timeout[4]),
|
| 922 |
|
|
|
| 923 |
|
|
//LOAD CMD
|
| 924 |
|
|
.load_wr(ch_load_wr[4]),
|
| 925 |
|
|
.load_wr_cycle(load_wr_cycle),
|
| 926 |
|
|
.load_wdata(load_wdata),
|
| 927 |
|
|
.load_req_in_prog(ch_load_req_in_prog[4]),
|
| 928 |
|
|
|
| 929 |
|
|
//CTRL
|
| 930 |
|
|
.ch_active(ch_active[4]),
|
| 931 |
|
|
.ch_rd_active(ch_rd_active[4]),
|
| 932 |
|
|
.ch_wr_active(ch_wr_active[4]),
|
| 933 |
|
|
|
| 934 |
|
|
//RD CTRL
|
| 935 |
|
|
.rd_burst_start(ch_rd_burst_start[4]),
|
| 936 |
|
|
.rd_ready(ch_rd_ready[4]),
|
| 937 |
|
|
.rd_burst_addr(ch_rd_burst_addr[32-1+32*4:32*4]),
|
| 938 |
|
|
.rd_burst_size(ch_rd_burst_size[7-1+7*4:7*4]),
|
| 939 |
|
|
.rd_tokens(ch_rd_tokens[`TOKEN_BITS-1+`TOKEN_BITS*4:`TOKEN_BITS*4]),
|
| 940 |
|
|
.rd_port_num(ch_rd_port_num[4]),
|
| 941 |
|
|
.rd_periph_delay(ch_rd_periph_delay[`DELAY_BITS-1+`DELAY_BITS*4:`DELAY_BITS*4]),
|
| 942 |
|
|
.rd_clr_valid(ch_rd_clr_valid[4]),
|
| 943 |
|
|
|
| 944 |
|
|
//WR CTRL
|
| 945 |
|
|
.wr_burst_start(ch_wr_burst_start[4]),
|
| 946 |
|
|
.wr_ready(ch_wr_ready[4]),
|
| 947 |
|
|
.wr_burst_addr(ch_wr_burst_addr[32-1+32*4:32*4]),
|
| 948 |
|
|
.wr_burst_size(ch_wr_burst_size[7-1+7*4:7*4]),
|
| 949 |
|
|
.wr_tokens(ch_wr_tokens[`TOKEN_BITS-1+`TOKEN_BITS*4:`TOKEN_BITS*4]),
|
| 950 |
|
|
.wr_port_num(ch_wr_port_num[4]),
|
| 951 |
|
|
.wr_periph_delay(ch_wr_periph_delay[`DELAY_BITS-1+`DELAY_BITS*4:`DELAY_BITS*4]),
|
| 952 |
|
|
.wr_clr_valid(ch_wr_clr_valid[4]),
|
| 953 |
|
|
|
| 954 |
|
|
//FIFO
|
| 955 |
|
|
.fifo_wr(ch_fifo_wr[4]),
|
| 956 |
|
|
.fifo_wdata(fifo_wdata),
|
| 957 |
|
|
.fifo_wsize(fifo_wsize),
|
| 958 |
|
|
.fifo_rd(ch_fifo_rd[4]),
|
| 959 |
|
|
.fifo_rsize(fifo_rsize),
|
| 960 |
|
|
.fifo_rd_valid(ch_fifo_rd_valid[4]),
|
| 961 |
|
|
.fifo_rdata(ch_fifo_rdata[(32-1)+32*4:32*4]),
|
| 962 |
|
|
.fifo_wr_ready(ch_fifo_wr_ready[4]),
|
| 963 |
|
|
|
| 964 |
|
|
.joint_mode(joint_mode),
|
| 965 |
|
|
.joint_remote(joint_remote),
|
| 966 |
|
|
.rd_page_cross(ch_rd_page_cross[4]),
|
| 967 |
|
|
.wr_page_cross(ch_wr_page_cross[4]),
|
| 968 |
|
|
.joint_in_prog(ch_joint_in_prog[4]),
|
| 969 |
|
|
.joint_not_in_prog(ch_joint_not_in_prog[4]),
|
| 970 |
|
|
.joint_mux_in_prog(ch_joint_mux_in_prog[4]),
|
| 971 |
|
|
.joint_req(ch_joint_req[4]),
|
| 972 |
|
|
|
| 973 |
|
|
.ch_start(ch_start[4]),
|
| 974 |
|
|
|
| 975 |
|
|
//INT
|
| 976 |
|
|
.int_all_proc(ch_int_all_proc[1-1+(1*4):1*4])
|
| 977 |
|
|
);
|
| 978 |
|
|
|
| 979 |
|
|
dma_ahb32_core0_ch_empty dma_ahb32_core0_ch_empty5 (
|
| 980 |
|
|
.clk(clk),
|
| 981 |
|
|
.reset(reset),
|
| 982 |
|
|
.scan_en(scan_en),
|
| 983 |
|
|
.idle(ch_idle[5]),
|
| 984 |
|
|
|
| 985 |
|
|
//APB
|
| 986 |
|
|
.pclk(pclk),
|
| 987 |
|
|
.clken(clken),
|
| 988 |
|
|
.pclken(pclken),
|
| 989 |
|
|
.psel(ch_psel[5]),
|
| 990 |
|
|
.penable(penable),
|
| 991 |
|
|
.paddr(paddr[7:0]),
|
| 992 |
|
|
.pwrite(pwrite),
|
| 993 |
|
|
.pwdata(pwdata),
|
| 994 |
|
|
.prdata(ch_prdata[31+32*5:32*5]),
|
| 995 |
|
|
.pslverr(ch_pslverr[5]),
|
| 996 |
|
|
|
| 997 |
|
|
//PERIPH
|
| 998 |
|
|
.periph_tx_req(periph_tx_req),
|
| 999 |
|
|
.periph_tx_clr(ch_periph_tx_clr[31*5+31-1:31*5]),
|
| 1000 |
|
|
.periph_rx_req(periph_rx_req),
|
| 1001 |
|
|
.periph_rx_clr(ch_periph_rx_clr[31*5+31-1:31*5]),
|
| 1002 |
|
|
|
| 1003 |
|
|
//RD AXIM
|
| 1004 |
|
|
.rd_cmd_split(ch_rd_cmd_split[5]),
|
| 1005 |
|
|
.rd_cmd_line(ch_rd_cmd_line[5]),
|
| 1006 |
|
|
.rd_clr_line(ch_rd_clr_line[5]),
|
| 1007 |
|
|
.rd_clr(ch_rd_clr[5]),
|
| 1008 |
|
|
.rd_clr_load(ch_rd_clr_load[5]),
|
| 1009 |
|
|
.rd_slverr(ch_rd_slverr[5]),
|
| 1010 |
|
|
.rd_decerr(ch_rd_decerr[5]),
|
| 1011 |
|
|
.rd_line_cmd(ch_rd_line_cmd[5]),
|
| 1012 |
|
|
.rd_go_next_line(ch_rd_go_next_line[5]),
|
| 1013 |
|
|
.rd_transfer(ch_rd_transfer[5]),
|
| 1014 |
|
|
.rd_transfer_size(rd_transfer_size),
|
| 1015 |
|
|
.rd_clr_stall(ch_rd_clr_stall[5]),
|
| 1016 |
|
|
|
| 1017 |
|
|
//WR AXIM
|
| 1018 |
|
|
.wr_cmd_split(ch_wr_cmd_split[5]),
|
| 1019 |
|
|
.wr_cmd_pending(ch_wr_cmd_pending[5]),
|
| 1020 |
|
|
.wr_clr_line(ch_wr_clr_line[5]),
|
| 1021 |
|
|
.wr_clr(ch_wr_clr[5]),
|
| 1022 |
|
|
.wr_clr_last(ch_wr_clr_last[5]),
|
| 1023 |
|
|
.wr_slverr(ch_wr_slverr[5]),
|
| 1024 |
|
|
.wr_decerr(ch_wr_decerr[5]),
|
| 1025 |
|
|
.wr_last_cmd(ch_wr_last_cmd[5]),
|
| 1026 |
|
|
.wr_line_cmd(ch_wr_line_cmd[5]),
|
| 1027 |
|
|
.wr_go_next_line(ch_wr_go_next_line[5]),
|
| 1028 |
|
|
.wr_transfer(ch_wr_transfer[5]),
|
| 1029 |
|
|
.wr_transfer_size(wr_transfer_size),
|
| 1030 |
|
|
.wr_next_size(wr_next_size),
|
| 1031 |
|
|
.wr_clr_stall(ch_wr_clr_stall[5]),
|
| 1032 |
|
|
|
| 1033 |
|
|
.timeout_aw(ch_timeout_aw[5]),
|
| 1034 |
|
|
.timeout_w(ch_timeout_w[5]),
|
| 1035 |
|
|
.timeout_ar(ch_timeout_ar[5]),
|
| 1036 |
|
|
.wdt_timeout(ch_wdt_timeout[5]),
|
| 1037 |
|
|
|
| 1038 |
|
|
//LOAD CMD
|
| 1039 |
|
|
.load_wr(ch_load_wr[5]),
|
| 1040 |
|
|
.load_wr_cycle(load_wr_cycle),
|
| 1041 |
|
|
.load_wdata(load_wdata),
|
| 1042 |
|
|
.load_req_in_prog(ch_load_req_in_prog[5]),
|
| 1043 |
|
|
|
| 1044 |
|
|
//CTRL
|
| 1045 |
|
|
.ch_active(ch_active[5]),
|
| 1046 |
|
|
.ch_rd_active(ch_rd_active[5]),
|
| 1047 |
|
|
.ch_wr_active(ch_wr_active[5]),
|
| 1048 |
|
|
|
| 1049 |
|
|
//RD CTRL
|
| 1050 |
|
|
.rd_burst_start(ch_rd_burst_start[5]),
|
| 1051 |
|
|
.rd_ready(ch_rd_ready[5]),
|
| 1052 |
|
|
.rd_burst_addr(ch_rd_burst_addr[32-1+32*5:32*5]),
|
| 1053 |
|
|
.rd_burst_size(ch_rd_burst_size[7-1+7*5:7*5]),
|
| 1054 |
|
|
.rd_tokens(ch_rd_tokens[`TOKEN_BITS-1+`TOKEN_BITS*5:`TOKEN_BITS*5]),
|
| 1055 |
|
|
.rd_port_num(ch_rd_port_num[5]),
|
| 1056 |
|
|
.rd_periph_delay(ch_rd_periph_delay[`DELAY_BITS-1+`DELAY_BITS*5:`DELAY_BITS*5]),
|
| 1057 |
|
|
.rd_clr_valid(ch_rd_clr_valid[5]),
|
| 1058 |
|
|
|
| 1059 |
|
|
//WR CTRL
|
| 1060 |
|
|
.wr_burst_start(ch_wr_burst_start[5]),
|
| 1061 |
|
|
.wr_ready(ch_wr_ready[5]),
|
| 1062 |
|
|
.wr_burst_addr(ch_wr_burst_addr[32-1+32*5:32*5]),
|
| 1063 |
|
|
.wr_burst_size(ch_wr_burst_size[7-1+7*5:7*5]),
|
| 1064 |
|
|
.wr_tokens(ch_wr_tokens[`TOKEN_BITS-1+`TOKEN_BITS*5:`TOKEN_BITS*5]),
|
| 1065 |
|
|
.wr_port_num(ch_wr_port_num[5]),
|
| 1066 |
|
|
.wr_periph_delay(ch_wr_periph_delay[`DELAY_BITS-1+`DELAY_BITS*5:`DELAY_BITS*5]),
|
| 1067 |
|
|
.wr_clr_valid(ch_wr_clr_valid[5]),
|
| 1068 |
|
|
|
| 1069 |
|
|
//FIFO
|
| 1070 |
|
|
.fifo_wr(ch_fifo_wr[5]),
|
| 1071 |
|
|
.fifo_wdata(fifo_wdata),
|
| 1072 |
|
|
.fifo_wsize(fifo_wsize),
|
| 1073 |
|
|
.fifo_rd(ch_fifo_rd[5]),
|
| 1074 |
|
|
.fifo_rsize(fifo_rsize),
|
| 1075 |
|
|
.fifo_rd_valid(ch_fifo_rd_valid[5]),
|
| 1076 |
|
|
.fifo_rdata(ch_fifo_rdata[(32-1)+32*5:32*5]),
|
| 1077 |
|
|
.fifo_wr_ready(ch_fifo_wr_ready[5]),
|
| 1078 |
|
|
|
| 1079 |
|
|
.joint_mode(joint_mode),
|
| 1080 |
|
|
.joint_remote(joint_remote),
|
| 1081 |
|
|
.rd_page_cross(ch_rd_page_cross[5]),
|
| 1082 |
|
|
.wr_page_cross(ch_wr_page_cross[5]),
|
| 1083 |
|
|
.joint_in_prog(ch_joint_in_prog[5]),
|
| 1084 |
|
|
.joint_not_in_prog(ch_joint_not_in_prog[5]),
|
| 1085 |
|
|
.joint_mux_in_prog(ch_joint_mux_in_prog[5]),
|
| 1086 |
|
|
.joint_req(ch_joint_req[5]),
|
| 1087 |
|
|
|
| 1088 |
|
|
.ch_start(ch_start[5]),
|
| 1089 |
|
|
|
| 1090 |
|
|
//INT
|
| 1091 |
|
|
.int_all_proc(ch_int_all_proc[1-1+(1*5):1*5])
|
| 1092 |
|
|
);
|
| 1093 |
|
|
|
| 1094 |
|
|
dma_ahb32_core0_ch_empty dma_ahb32_core0_ch_empty6 (
|
| 1095 |
|
|
.clk(clk),
|
| 1096 |
|
|
.reset(reset),
|
| 1097 |
|
|
.scan_en(scan_en),
|
| 1098 |
|
|
.idle(ch_idle[6]),
|
| 1099 |
|
|
|
| 1100 |
|
|
//APB
|
| 1101 |
|
|
.pclk(pclk),
|
| 1102 |
|
|
.clken(clken),
|
| 1103 |
|
|
.pclken(pclken),
|
| 1104 |
|
|
.psel(ch_psel[6]),
|
| 1105 |
|
|
.penable(penable),
|
| 1106 |
|
|
.paddr(paddr[7:0]),
|
| 1107 |
|
|
.pwrite(pwrite),
|
| 1108 |
|
|
.pwdata(pwdata),
|
| 1109 |
|
|
.prdata(ch_prdata[31+32*6:32*6]),
|
| 1110 |
|
|
.pslverr(ch_pslverr[6]),
|
| 1111 |
|
|
|
| 1112 |
|
|
//PERIPH
|
| 1113 |
|
|
.periph_tx_req(periph_tx_req),
|
| 1114 |
|
|
.periph_tx_clr(ch_periph_tx_clr[31*6+31-1:31*6]),
|
| 1115 |
|
|
.periph_rx_req(periph_rx_req),
|
| 1116 |
|
|
.periph_rx_clr(ch_periph_rx_clr[31*6+31-1:31*6]),
|
| 1117 |
|
|
|
| 1118 |
|
|
//RD AXIM
|
| 1119 |
|
|
.rd_cmd_split(ch_rd_cmd_split[6]),
|
| 1120 |
|
|
.rd_cmd_line(ch_rd_cmd_line[6]),
|
| 1121 |
|
|
.rd_clr_line(ch_rd_clr_line[6]),
|
| 1122 |
|
|
.rd_clr(ch_rd_clr[6]),
|
| 1123 |
|
|
.rd_clr_load(ch_rd_clr_load[6]),
|
| 1124 |
|
|
.rd_slverr(ch_rd_slverr[6]),
|
| 1125 |
|
|
.rd_decerr(ch_rd_decerr[6]),
|
| 1126 |
|
|
.rd_line_cmd(ch_rd_line_cmd[6]),
|
| 1127 |
|
|
.rd_go_next_line(ch_rd_go_next_line[6]),
|
| 1128 |
|
|
.rd_transfer(ch_rd_transfer[6]),
|
| 1129 |
|
|
.rd_transfer_size(rd_transfer_size),
|
| 1130 |
|
|
.rd_clr_stall(ch_rd_clr_stall[6]),
|
| 1131 |
|
|
|
| 1132 |
|
|
//WR AXIM
|
| 1133 |
|
|
.wr_cmd_split(ch_wr_cmd_split[6]),
|
| 1134 |
|
|
.wr_cmd_pending(ch_wr_cmd_pending[6]),
|
| 1135 |
|
|
.wr_clr_line(ch_wr_clr_line[6]),
|
| 1136 |
|
|
.wr_clr(ch_wr_clr[6]),
|
| 1137 |
|
|
.wr_clr_last(ch_wr_clr_last[6]),
|
| 1138 |
|
|
.wr_slverr(ch_wr_slverr[6]),
|
| 1139 |
|
|
.wr_decerr(ch_wr_decerr[6]),
|
| 1140 |
|
|
.wr_last_cmd(ch_wr_last_cmd[6]),
|
| 1141 |
|
|
.wr_line_cmd(ch_wr_line_cmd[6]),
|
| 1142 |
|
|
.wr_go_next_line(ch_wr_go_next_line[6]),
|
| 1143 |
|
|
.wr_transfer(ch_wr_transfer[6]),
|
| 1144 |
|
|
.wr_transfer_size(wr_transfer_size),
|
| 1145 |
|
|
.wr_next_size(wr_next_size),
|
| 1146 |
|
|
.wr_clr_stall(ch_wr_clr_stall[6]),
|
| 1147 |
|
|
|
| 1148 |
|
|
.timeout_aw(ch_timeout_aw[6]),
|
| 1149 |
|
|
.timeout_w(ch_timeout_w[6]),
|
| 1150 |
|
|
.timeout_ar(ch_timeout_ar[6]),
|
| 1151 |
|
|
.wdt_timeout(ch_wdt_timeout[6]),
|
| 1152 |
|
|
|
| 1153 |
|
|
//LOAD CMD
|
| 1154 |
|
|
.load_wr(ch_load_wr[6]),
|
| 1155 |
|
|
.load_wr_cycle(load_wr_cycle),
|
| 1156 |
|
|
.load_wdata(load_wdata),
|
| 1157 |
|
|
.load_req_in_prog(ch_load_req_in_prog[6]),
|
| 1158 |
|
|
|
| 1159 |
|
|
//CTRL
|
| 1160 |
|
|
.ch_active(ch_active[6]),
|
| 1161 |
|
|
.ch_rd_active(ch_rd_active[6]),
|
| 1162 |
|
|
.ch_wr_active(ch_wr_active[6]),
|
| 1163 |
|
|
|
| 1164 |
|
|
//RD CTRL
|
| 1165 |
|
|
.rd_burst_start(ch_rd_burst_start[6]),
|
| 1166 |
|
|
.rd_ready(ch_rd_ready[6]),
|
| 1167 |
|
|
.rd_burst_addr(ch_rd_burst_addr[32-1+32*6:32*6]),
|
| 1168 |
|
|
.rd_burst_size(ch_rd_burst_size[7-1+7*6:7*6]),
|
| 1169 |
|
|
.rd_tokens(ch_rd_tokens[`TOKEN_BITS-1+`TOKEN_BITS*6:`TOKEN_BITS*6]),
|
| 1170 |
|
|
.rd_port_num(ch_rd_port_num[6]),
|
| 1171 |
|
|
.rd_periph_delay(ch_rd_periph_delay[`DELAY_BITS-1+`DELAY_BITS*6:`DELAY_BITS*6]),
|
| 1172 |
|
|
.rd_clr_valid(ch_rd_clr_valid[6]),
|
| 1173 |
|
|
|
| 1174 |
|
|
//WR CTRL
|
| 1175 |
|
|
.wr_burst_start(ch_wr_burst_start[6]),
|
| 1176 |
|
|
.wr_ready(ch_wr_ready[6]),
|
| 1177 |
|
|
.wr_burst_addr(ch_wr_burst_addr[32-1+32*6:32*6]),
|
| 1178 |
|
|
.wr_burst_size(ch_wr_burst_size[7-1+7*6:7*6]),
|
| 1179 |
|
|
.wr_tokens(ch_wr_tokens[`TOKEN_BITS-1+`TOKEN_BITS*6:`TOKEN_BITS*6]),
|
| 1180 |
|
|
.wr_port_num(ch_wr_port_num[6]),
|
| 1181 |
|
|
.wr_periph_delay(ch_wr_periph_delay[`DELAY_BITS-1+`DELAY_BITS*6:`DELAY_BITS*6]),
|
| 1182 |
|
|
.wr_clr_valid(ch_wr_clr_valid[6]),
|
| 1183 |
|
|
|
| 1184 |
|
|
//FIFO
|
| 1185 |
|
|
.fifo_wr(ch_fifo_wr[6]),
|
| 1186 |
|
|
.fifo_wdata(fifo_wdata),
|
| 1187 |
|
|
.fifo_wsize(fifo_wsize),
|
| 1188 |
|
|
.fifo_rd(ch_fifo_rd[6]),
|
| 1189 |
|
|
.fifo_rsize(fifo_rsize),
|
| 1190 |
|
|
.fifo_rd_valid(ch_fifo_rd_valid[6]),
|
| 1191 |
|
|
.fifo_rdata(ch_fifo_rdata[(32-1)+32*6:32*6]),
|
| 1192 |
|
|
.fifo_wr_ready(ch_fifo_wr_ready[6]),
|
| 1193 |
|
|
|
| 1194 |
|
|
.joint_mode(joint_mode),
|
| 1195 |
|
|
.joint_remote(joint_remote),
|
| 1196 |
|
|
.rd_page_cross(ch_rd_page_cross[6]),
|
| 1197 |
|
|
.wr_page_cross(ch_wr_page_cross[6]),
|
| 1198 |
|
|
.joint_in_prog(ch_joint_in_prog[6]),
|
| 1199 |
|
|
.joint_not_in_prog(ch_joint_not_in_prog[6]),
|
| 1200 |
|
|
.joint_mux_in_prog(ch_joint_mux_in_prog[6]),
|
| 1201 |
|
|
.joint_req(ch_joint_req[6]),
|
| 1202 |
|
|
|
| 1203 |
|
|
.ch_start(ch_start[6]),
|
| 1204 |
|
|
|
| 1205 |
|
|
//INT
|
| 1206 |
|
|
.int_all_proc(ch_int_all_proc[1-1+(1*6):1*6])
|
| 1207 |
|
|
);
|
| 1208 |
|
|
|
| 1209 |
|
|
dma_ahb32_core0_ch_empty dma_ahb32_core0_ch_empty7 (
|
| 1210 |
|
|
.clk(clk),
|
| 1211 |
|
|
.reset(reset),
|
| 1212 |
|
|
.scan_en(scan_en),
|
| 1213 |
|
|
.idle(ch_idle[7]),
|
| 1214 |
|
|
|
| 1215 |
|
|
//APB
|
| 1216 |
|
|
.pclk(pclk),
|
| 1217 |
|
|
.clken(clken),
|
| 1218 |
|
|
.pclken(pclken),
|
| 1219 |
|
|
.psel(ch_psel[7]),
|
| 1220 |
|
|
.penable(penable),
|
| 1221 |
|
|
.paddr(paddr[7:0]),
|
| 1222 |
|
|
.pwrite(pwrite),
|
| 1223 |
|
|
.pwdata(pwdata),
|
| 1224 |
|
|
.prdata(ch_prdata[31+32*7:32*7]),
|
| 1225 |
|
|
.pslverr(ch_pslverr[7]),
|
| 1226 |
|
|
|
| 1227 |
|
|
//PERIPH
|
| 1228 |
|
|
.periph_tx_req(periph_tx_req),
|
| 1229 |
|
|
.periph_tx_clr(ch_periph_tx_clr[31*7+31-1:31*7]),
|
| 1230 |
|
|
.periph_rx_req(periph_rx_req),
|
| 1231 |
|
|
.periph_rx_clr(ch_periph_rx_clr[31*7+31-1:31*7]),
|
| 1232 |
|
|
|
| 1233 |
|
|
//RD AXIM
|
| 1234 |
|
|
.rd_cmd_split(ch_rd_cmd_split[7]),
|
| 1235 |
|
|
.rd_cmd_line(ch_rd_cmd_line[7]),
|
| 1236 |
|
|
.rd_clr_line(ch_rd_clr_line[7]),
|
| 1237 |
|
|
.rd_clr(ch_rd_clr[7]),
|
| 1238 |
|
|
.rd_clr_load(ch_rd_clr_load[7]),
|
| 1239 |
|
|
.rd_slverr(ch_rd_slverr[7]),
|
| 1240 |
|
|
.rd_decerr(ch_rd_decerr[7]),
|
| 1241 |
|
|
.rd_line_cmd(ch_rd_line_cmd[7]),
|
| 1242 |
|
|
.rd_go_next_line(ch_rd_go_next_line[7]),
|
| 1243 |
|
|
.rd_transfer(ch_rd_transfer[7]),
|
| 1244 |
|
|
.rd_transfer_size(rd_transfer_size),
|
| 1245 |
|
|
.rd_clr_stall(ch_rd_clr_stall[7]),
|
| 1246 |
|
|
|
| 1247 |
|
|
//WR AXIM
|
| 1248 |
|
|
.wr_cmd_split(ch_wr_cmd_split[7]),
|
| 1249 |
|
|
.wr_cmd_pending(ch_wr_cmd_pending[7]),
|
| 1250 |
|
|
.wr_clr_line(ch_wr_clr_line[7]),
|
| 1251 |
|
|
.wr_clr(ch_wr_clr[7]),
|
| 1252 |
|
|
.wr_clr_last(ch_wr_clr_last[7]),
|
| 1253 |
|
|
.wr_slverr(ch_wr_slverr[7]),
|
| 1254 |
|
|
.wr_decerr(ch_wr_decerr[7]),
|
| 1255 |
|
|
.wr_last_cmd(ch_wr_last_cmd[7]),
|
| 1256 |
|
|
.wr_line_cmd(ch_wr_line_cmd[7]),
|
| 1257 |
|
|
.wr_go_next_line(ch_wr_go_next_line[7]),
|
| 1258 |
|
|
.wr_transfer(ch_wr_transfer[7]),
|
| 1259 |
|
|
.wr_transfer_size(wr_transfer_size),
|
| 1260 |
|
|
.wr_next_size(wr_next_size),
|
| 1261 |
|
|
.wr_clr_stall(ch_wr_clr_stall[7]),
|
| 1262 |
|
|
|
| 1263 |
|
|
.timeout_aw(ch_timeout_aw[7]),
|
| 1264 |
|
|
.timeout_w(ch_timeout_w[7]),
|
| 1265 |
|
|
.timeout_ar(ch_timeout_ar[7]),
|
| 1266 |
|
|
.wdt_timeout(ch_wdt_timeout[7]),
|
| 1267 |
|
|
|
| 1268 |
|
|
//LOAD CMD
|
| 1269 |
|
|
.load_wr(ch_load_wr[7]),
|
| 1270 |
|
|
.load_wr_cycle(load_wr_cycle),
|
| 1271 |
|
|
.load_wdata(load_wdata),
|
| 1272 |
|
|
.load_req_in_prog(ch_load_req_in_prog[7]),
|
| 1273 |
|
|
|
| 1274 |
|
|
//CTRL
|
| 1275 |
|
|
.ch_active(ch_active[7]),
|
| 1276 |
|
|
.ch_rd_active(ch_rd_active[7]),
|
| 1277 |
|
|
.ch_wr_active(ch_wr_active[7]),
|
| 1278 |
|
|
|
| 1279 |
|
|
//RD CTRL
|
| 1280 |
|
|
.rd_burst_start(ch_rd_burst_start[7]),
|
| 1281 |
|
|
.rd_ready(ch_rd_ready[7]),
|
| 1282 |
|
|
.rd_burst_addr(ch_rd_burst_addr[32-1+32*7:32*7]),
|
| 1283 |
|
|
.rd_burst_size(ch_rd_burst_size[7-1+7*7:7*7]),
|
| 1284 |
|
|
.rd_tokens(ch_rd_tokens[`TOKEN_BITS-1+`TOKEN_BITS*7:`TOKEN_BITS*7]),
|
| 1285 |
|
|
.rd_port_num(ch_rd_port_num[7]),
|
| 1286 |
|
|
.rd_periph_delay(ch_rd_periph_delay[`DELAY_BITS-1+`DELAY_BITS*7:`DELAY_BITS*7]),
|
| 1287 |
|
|
.rd_clr_valid(ch_rd_clr_valid[7]),
|
| 1288 |
|
|
|
| 1289 |
|
|
//WR CTRL
|
| 1290 |
|
|
.wr_burst_start(ch_wr_burst_start[7]),
|
| 1291 |
|
|
.wr_ready(ch_wr_ready[7]),
|
| 1292 |
|
|
.wr_burst_addr(ch_wr_burst_addr[32-1+32*7:32*7]),
|
| 1293 |
|
|
.wr_burst_size(ch_wr_burst_size[7-1+7*7:7*7]),
|
| 1294 |
|
|
.wr_tokens(ch_wr_tokens[`TOKEN_BITS-1+`TOKEN_BITS*7:`TOKEN_BITS*7]),
|
| 1295 |
|
|
.wr_port_num(ch_wr_port_num[7]),
|
| 1296 |
|
|
.wr_periph_delay(ch_wr_periph_delay[`DELAY_BITS-1+`DELAY_BITS*7:`DELAY_BITS*7]),
|
| 1297 |
|
|
.wr_clr_valid(ch_wr_clr_valid[7]),
|
| 1298 |
|
|
|
| 1299 |
|
|
//FIFO
|
| 1300 |
|
|
.fifo_wr(ch_fifo_wr[7]),
|
| 1301 |
|
|
.fifo_wdata(fifo_wdata),
|
| 1302 |
|
|
.fifo_wsize(fifo_wsize),
|
| 1303 |
|
|
.fifo_rd(ch_fifo_rd[7]),
|
| 1304 |
|
|
.fifo_rsize(fifo_rsize),
|
| 1305 |
|
|
.fifo_rd_valid(ch_fifo_rd_valid[7]),
|
| 1306 |
|
|
.fifo_rdata(ch_fifo_rdata[(32-1)+32*7:32*7]),
|
| 1307 |
|
|
.fifo_wr_ready(ch_fifo_wr_ready[7]),
|
| 1308 |
|
|
|
| 1309 |
|
|
.joint_mode(joint_mode),
|
| 1310 |
|
|
.joint_remote(joint_remote),
|
| 1311 |
|
|
.rd_page_cross(ch_rd_page_cross[7]),
|
| 1312 |
|
|
.wr_page_cross(ch_wr_page_cross[7]),
|
| 1313 |
|
|
.joint_in_prog(ch_joint_in_prog[7]),
|
| 1314 |
|
|
.joint_not_in_prog(ch_joint_not_in_prog[7]),
|
| 1315 |
|
|
.joint_mux_in_prog(ch_joint_mux_in_prog[7]),
|
| 1316 |
|
|
.joint_req(ch_joint_req[7]),
|
| 1317 |
|
|
|
| 1318 |
|
|
.ch_start(ch_start[7]),
|
| 1319 |
|
|
|
| 1320 |
|
|
//INT
|
| 1321 |
|
|
.int_all_proc(ch_int_all_proc[1-1+(1*7):1*7])
|
| 1322 |
|
|
);
|
| 1323 |
|
|
|
| 1324 |
|
|
|
| 1325 |
|
|
|
| 1326 |
|
|
endmodule
|
| 1327 |
|
|
|
| 1328 |
|
|
|
| 1329 |
|
|
|
