OpenCores
URL https://opencores.org/ocsvn/dma_ahb/dma_ahb/trunk

Subversion Repositories dma_ahb

[/] [dma_ahb/] [trunk/] [src/] [dma_ahb32/] [dma_ahb32_reg.v] - Blame information for rev 2

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 eyalhoc
//---------------------------------------------------------
2
//-- File generated by RobustVerilog parser
3
//-- Version: 1.0
4
//-- Invoked Fri Mar 25 23:31:21 2011
5
//--
6
//-- Source file: dma_reg.v
7
//---------------------------------------------------------
8
 
9
 
10
 
11
module dma_ahb32_reg(clk,reset,pclken,psel,penable,paddr,pwrite,pwdata,prdata,pslverr,core0_idle,ch_int_all_proc0,int_all_proc,core0_clkdiv,core0_ch_start,joint_mode0,rd_prio_top0,rd_prio_high0,rd_prio_top_num0,rd_prio_high_num0,wr_prio_top0,wr_prio_high0,wr_prio_top_num0,wr_prio_high_num0,periph_rx_req_reg,periph_tx_req_reg,periph_rx_clr,periph_tx_clr);
12
 
13
   input                       clk;
14
   input                   reset;
15
 
16
   input                   pclken;
17
   input                   psel;
18
   input                   penable;
19
   input [7:0]                   paddr;
20
   input                   pwrite;
21
   input [31:0]               pwdata;
22
   output [31:0]               prdata;
23
   output                   pslverr;
24
 
25
   input                   core0_idle;
26
   input [8*1-1:0]             ch_int_all_proc0;
27
   output [1-1:0]              int_all_proc;
28
   output [3:0]               core0_clkdiv;
29
   output [7:0]               core0_ch_start;
30
   output                   joint_mode0;
31
   output                   rd_prio_top0;
32
   output                   rd_prio_high0;
33
   output [2:0]               rd_prio_top_num0;
34
   output [2:0]               rd_prio_high_num0;
35
   output                   wr_prio_top0;
36
   output                   wr_prio_high0;
37
   output [2:0]               wr_prio_top_num0;
38
   output [2:0]               wr_prio_high_num0;
39
   output [31:1]               periph_rx_req_reg;
40
   output [31:1]               periph_tx_req_reg;
41
   input [31:1]               periph_rx_clr;
42
   input [31:1]               periph_tx_clr;
43
 
44
`include "dma_ahb32_reg_params.v"
45
 
46
 
47
   wire [31:0]                   user_def_stat;
48
   wire [31:0]                   user_def0_stat0;
49
   wire [31:0]                   user_def0_stat1;
50
 
51
   wire                   user_def_proj;
52
   wire [3:0]                   user_def_proc_num;
53
   wire                   user_def_dual_core;
54
   wire                   user_def_ic;
55
   wire                   user_def_ic_dual_port;
56
   wire                   user_def_clkgate;
57
   wire                   user_def_port0_mux;
58
   wire                   user_def_port1_mux;
59
 
60
   wire                               wr_joint0;
61
   wire                               wr_clkdiv0;
62
   wire                               wr_start0;
63
   wire                               wr_prio0;
64
 
65
   wire [7:0]                         proc0_int_stat0;
66
   wire [15:0]                        proc0_int_stat;
67
   wire                               proc0_int;
68
   wire [1-1:0]                int_all_proc_pre;
69
   reg [1-1:0]                 int_all_proc;
70
 
71
 
72
   wire                   wr_periph_rx;
73
   wire                   wr_periph_tx;
74
   reg [31:1]                   periph_rx_req_reg;
75
   reg [31:1]                   periph_tx_req_reg;
76
 
77
   wire [7:0]                   gpaddr;
78
   wire                   gpwrite;
79
   wire                   gpread;
80
 
81
   reg [31:0]                   prdata_pre;
82
   reg                       pslverr_pre;
83
   reg [31:0]                   prdata;
84
   reg                       pslverr;
85
 
86
 
87
   assign                              wr_joint0  = gpwrite & gpaddr == CORE0_JOINT;
88
   assign                              wr_clkdiv0 = gpwrite & gpaddr == CORE0_CLKDIV;
89
   assign                              wr_start0  = gpwrite & gpaddr == CORE0_START;
90
   assign                              wr_prio0   = gpwrite & gpaddr == CORE0_PRIO;
91
 
92
dma_ahb32_reg_core0 dma_ahb32_reg_core0(
93
                               .clk(clk),
94
                           .reset(reset),
95
                                   .wr_joint(wr_joint0),
96
                                   .wr_clkdiv(wr_clkdiv0),
97
                                   .wr_start(wr_start0),
98
                                   .wr_prio(wr_prio0),
99
                                   .pwdata(pwdata),
100
                                   .clkdiv(core0_clkdiv),
101
                                .ch_start(core0_ch_start),
102
                           .joint_mode(joint_mode0),
103
                           .rd_prio_top(rd_prio_top0),
104
                           .rd_prio_high(rd_prio_high0),
105
                                .rd_prio_top_num(rd_prio_top_num0),
106
                                .rd_prio_high_num(rd_prio_high_num0),
107
                           .wr_prio_top(wr_prio_top0),
108
                           .wr_prio_high(wr_prio_high0),
109
                                .wr_prio_top_num(wr_prio_top_num0),
110
                                .wr_prio_high_num(wr_prio_high_num0),
111
                                   .user_def_stat0(user_def0_stat0),
112
                                   .user_def_stat1(user_def0_stat1),
113
                                   .ch_int_all_proc(ch_int_all_proc0),
114
                                   .proc0_int_stat(proc0_int_stat0)
115
                                   );
116
 
117
 
118
   assign                   user_def_proj             = 1;
119
   assign                   user_def_proc_num         = 1;
120
   assign                   user_def_dual_core        = 0;
121
   assign                   user_def_ic               = 0;
122
   assign                   user_def_ic_dual_port     = 0;
123
   assign                   user_def_clkgate          = 0;
124
   assign                   user_def_port0_mux        = 0;
125
   assign                   user_def_port1_mux        = 0;
126
 
127
   assign                   user_def_stat =
128
                             {user_def_proj,              //[31]
129
                              {20{1'b0}},                 //[30:11]
130
                              user_def_port1_mux,         //[10]
131
                              user_def_port0_mux,         //[9]
132
                              user_def_clkgate,           //[8]
133
                               user_def_ic_dual_port,      //[7]
134
                               user_def_ic,                //[6]
135
                               user_def_dual_core,         //[5]
136
                               1'b0,                       //[4]
137
                               user_def_proc_num           //[3:0]
138
                              };
139
 
140
 
141
 
142
 
143
 
144
   assign                   gpaddr      = {8{psel}} & paddr;
145
   assign                   gpwrite     = psel & (~penable) & pwrite;
146
   assign                   gpread      = psel & (~penable) & (~pwrite);
147
 
148
 
149
 
150
   assign              wr_periph_rx = gpwrite & gpaddr == PERIPH_RX_CTRL;
151
   assign              wr_periph_tx = gpwrite & gpaddr == PERIPH_TX_CTRL;
152
 
153
   always @(posedge clk or posedge reset)
154
     if (reset)
155
       periph_rx_req_reg <= #1 {31{1'b0}};
156
     else if (wr_periph_rx | (|periph_rx_clr))
157
       periph_rx_req_reg <= #1 ({31{wr_periph_rx}} & pwdata[31:1]) & (~periph_rx_clr);
158
 
159
   always @(posedge clk or posedge reset)
160
     if (reset)
161
       periph_tx_req_reg <= #1 {31{1'b0}};
162
     else if (wr_periph_tx | (|periph_tx_clr))
163
       periph_tx_req_reg <= #1 ({31{wr_periph_tx}} & pwdata[31:1]) & (~periph_tx_clr);
164
 
165
   assign                   proc0_int_stat = {proc0_int_stat0};
166
 
167
   assign                             proc0_int = |proc0_int_stat;
168
 
169
   assign                             int_all_proc_pre = {proc0_int};
170
 
171
   always @(posedge clk or posedge reset)
172
     if (reset)
173
       int_all_proc <= #1 {1{1'b0}};
174
     else
175
       int_all_proc <= #1 int_all_proc_pre;
176
 
177
 
178
   always @(*)
179
     begin
180
    prdata_pre  = {32{1'b0}};
181
 
182
    case (gpaddr)
183
      PROC0_STATUS             : prdata_pre  = {{16{1'b0}}, proc0_int_stat0};
184
 
185
      CORE0_JOINT              : prdata_pre  = {{31{1'b0}}, joint_mode0};
186
 
187
      CORE0_PRIO               : prdata_pre  = {{16{1'b0}}, wr_prio_high0, wr_prio_high_num0, wr_prio_top0, wr_prio_top_num0, rd_prio_high0, rd_prio_high_num0, rd_prio_top0, rd_prio_top_num0};
188
 
189
      CORE0_CLKDIV             : prdata_pre  = {{28{1'b0}}, core0_clkdiv};
190
 
191
      CORE0_START              : prdata_pre  = {32{1'b0}};
192
 
193
      PERIPH_RX_CTRL            : prdata_pre  = {periph_rx_req_reg, 1'b0};
194
      PERIPH_TX_CTRL            : prdata_pre  = {periph_tx_req_reg, 1'b0};
195
 
196
      IDLE                      : prdata_pre  = {{30{1'b0}}, core0_idle};
197
 
198
      USER_DEF_STAT             : prdata_pre  = user_def_stat;
199
      USER_DEF0_STAT0          : prdata_pre  = user_def0_stat0;
200
      USER_DEF0_STAT1          : prdata_pre  = user_def0_stat1;
201
 
202
      default                   : prdata_pre  = {32{1'b0}};
203
    endcase
204
     end
205
 
206
 
207
   always @(/*AUTOSENSE*/gpaddr or gpread or gpwrite or psel)
208
     begin
209
    pslverr_pre = 1'b0;
210
 
211
    case (gpaddr)
212
      PROC0_STATUS             : pslverr_pre = gpwrite; //read only
213
 
214
      CORE0_JOINT              : pslverr_pre = 1'b0;    //read and write
215
 
216
      CORE0_PRIO               : pslverr_pre = 1'b0;    //read and write  
217
 
218
      CORE0_CLKDIV             : pslverr_pre = 1'b0;    //read and write
219
 
220
      CORE0_START              : pslverr_pre = gpread;  //write only
221
 
222
      PERIPH_RX_CTRL            : pslverr_pre = 1'b0;    //read and write  
223
      PERIPH_TX_CTRL            : pslverr_pre = 1'b0;    //read and write  
224
 
225
      IDLE                      : pslverr_pre = gpwrite; //read only
226
 
227
      USER_DEF_STAT             : pslverr_pre = gpwrite; //read only
228
      USER_DEF0_STAT0          : pslverr_pre = gpwrite; //read only
229
      USER_DEF0_STAT1          : pslverr_pre = gpwrite; //read only
230
 
231
      default                   : pslverr_pre = psel;    //decode error
232
    endcase
233
     end
234
 
235
 
236
   always @(posedge clk or posedge reset)
237
     if (reset)
238
       prdata <= #1 {32{1'b0}};
239
     else if (gpread & pclken)
240
       prdata <= #1 prdata_pre;
241
     else if (pclken) //zero to allow or in apb_mux
242
       prdata <= #1 {32{1'b0}};
243
 
244
   always @(posedge clk or posedge reset)
245
     if (reset)
246
       pslverr <= #1 1'b0;
247
     else if ((gpread | gpwrite) & pclken)
248
       pslverr <= #1 pslverr_pre;
249
     else if (pclken)
250
       pslverr <= #1 1'b0;
251
 
252
 
253
endmodule
254
 
255
 
256
 
257
 
258
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.