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[/] [dma_ahb/] [trunk/] [src/] [dma_ahb64/] [dma_ahb64_core0_ch_fifo.v] - Blame information for rev 2

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1 2 eyalhoc
//---------------------------------------------------------
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//-- File generated by RobustVerilog parser
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//-- Version: 1.0
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//-- Invoked Fri Mar 25 23:33:02 2011
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//--
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//-- Source file: dma_ch_fifo.v
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//---------------------------------------------------------
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module dma_ahb64_core0_ch_fifo (CLK,WR,RD,WR_ADDR,RD_ADDR,DIN,BSEL,DOUT);
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   input                      CLK;
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   input               WR;
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   input               RD;
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   input [5-3-1:0] WR_ADDR;
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   input [5-3-1:0] RD_ADDR;
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   input [64-1:0]      DIN;
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   input [8-1:0]      BSEL;
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   output [64-1:0]     DOUT;
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   reg [64-1:0]           Mem [4-1:0];
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   wire [64-1:0]       BitSEL;
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   wire [64-1:0]       DIN_BitSEL;
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   reg [64-1:0]           DOUT;
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     assign               BitSEL = {{8{BSEL[7]}} , {8{BSEL[6]}} , {8{BSEL[5]}} , {8{BSEL[4]}} , {8{BSEL[3]}} , {8{BSEL[2]}} , {8{BSEL[1]}} , {8{BSEL[0]}}};
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   assign               DIN_BitSEL = (Mem[WR_ADDR] & ~BitSEL) | (DIN & BitSEL);
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   always @(posedge CLK)
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     if (WR)
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       Mem[WR_ADDR] <= #1 DIN_BitSEL;
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   always @(posedge CLK)
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     if (RD)
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       DOUT <= #1 Mem[RD_ADDR];
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endmodule
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