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[/] [dp_components/] [trunk/] [dp_hold_input.vhd] - Blame information for rev 4

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-------------------------------------------------------------------------------
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--
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-- Copyright 2020
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-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
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-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
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-- 
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-- Licensed under the Apache License, Version 2.0 (the "License");
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-- you may not use this file except in compliance with the License.
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-- You may obtain a copy of the License at
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-- 
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--     http://www.apache.org/licenses/LICENSE-2.0
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-- 
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-- Unless required by applicable law or agreed to in writing, software
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-- distributed under the License is distributed on an "AS IS" BASIS,
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-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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-- See the License for the specific language governing permissions and
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-- limitations under the License.
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--
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-------------------------------------------------------------------------------
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LIBRARY IEEE, dp_pkg_lib;
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USE IEEE.std_logic_1164.all;
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USE dp_pkg_lib.dp_stream_pkg.ALL;
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-- Purpose:
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--   Hold the sink input
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-- Description:
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--   This dp_hold_input provides the necessary input logic to hold the input
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--   data and control to easily register the source output. Compared to
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--   dp_pipeling the dp_hold_input is the same except for the output register
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--   stage. In this way dp_hold_input can be used in a more complicated stream
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--   component where the output is not always the same as the input.
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--   The snk_in.valid and hold_in.valid are never high at the same time.
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--   If src_in.ready goes low while snk_in.valid is high then this snk_in.valid
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--   is held in hold_in.valid and the corresponding snk_in.data will get held
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--   in the external src_out_reg.data. When src_in.ready goes high again then
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--   the held data becomes valid via src_out_reg.valid and hold_in.valid goes
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--   low. Due to the RL=1 the next cycle the snk_in.valid from the sink may go
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--   high. The next_src_out control signals are equal to pend_src_out AND
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--   src_in.ready, so they can directly be assigned to src_out_reg.data if the
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--   snk_in.data needs to be passed on.
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--   The internal pend_src_out control signals are available outside, in
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--   addition to the next_src_out control signals, to support external control
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--   independent of src_in.ready. Use pend_scr_out instead of next_src_out
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--   to avoid combinatorial loop when src_in.ready depends on next_src_out.
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--   The pend_src_out signals are used to implement show ahead behaviour like
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--   with RL=0, but for RL=1. The input can then be stopped based on the snk_in
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--   data and later on continued again without losing this snk_in data, because
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--   it was held as described above.
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-- Remarks:
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-- . Ready latency = 1
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-- . Without flow control so when src_in.ready = '1' fixed, then dp_hold_input
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--   becomes void because the dp_hold_ctrl output then remains '0'.
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ENTITY dp_hold_input IS
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  PORT (
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    rst              : IN  STD_LOGIC;
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    clk              : IN  STD_LOGIC;
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    -- ST sink
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    snk_out          : OUT t_dp_siso;
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    snk_in           : IN  t_dp_sosi;
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    -- ST source
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    src_in           : IN  t_dp_siso;
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    next_src_out     : OUT t_dp_sosi;
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    pend_src_out     : OUT t_dp_sosi;  -- the SOSI data fields are the same as for next_src_out
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    src_out_reg      : IN  t_dp_sosi   -- uses only the SOSI data fields
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  );
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END dp_hold_input;
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ARCHITECTURE rtl OF dp_hold_input IS
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  SIGNAL i_pend_src_out : t_dp_sosi;
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  SIGNAL hold_in        : t_dp_sosi;  -- uses only the SOSI ctrl fields
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BEGIN
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  pend_src_out <= i_pend_src_out;
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  -- SISO:
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  snk_out <= src_in;  --  No change in ready latency, pass on xon frame level flow control
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  -- SOSI:
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  -- Take care of active snk_in.valid, snk_in.sync, snk_in.sop and snk_in.eop
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  -- when src_in.ready went low. If hold_in.valid would not be used for
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  -- pend_src_out.valid and next_src_out.valid, then the pipeline would still
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  -- work, but the valid snk_in.data that came when src_in.ready went low,
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  -- will then only get pushed out on the next valid snk_in.valid. Whereas
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  -- hold_in.valid ensures that it will get pushed out as soon as src_in.ready
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  -- goes high again. This is typically necessary in case of packetized data
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  -- where the eop of one packet should not have to wait for the valid (sop)
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  -- of a next packet to get pushed out.
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  u_hold_val : ENTITY work.dp_hold_ctrl
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  PORT MAP (
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    rst      => rst,
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    clk      => clk,
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    ready    => src_in.ready,
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    in_ctrl  => snk_in.valid,
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    hld_ctrl => hold_in.valid
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  );
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  u_hold_sync : ENTITY work.dp_hold_ctrl
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  PORT MAP (
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    rst      => rst,
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    clk      => clk,
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    ready    => src_in.ready,
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    in_ctrl  => snk_in.sync,
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    hld_ctrl => hold_in.sync
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  );
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  u_hold_sop : ENTITY work.dp_hold_ctrl
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  PORT MAP (
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    rst      => rst,
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    clk      => clk,
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    ready    => src_in.ready,
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    in_ctrl  => snk_in.sop,
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    hld_ctrl => hold_in.sop
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  );
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  u_hold_eop : ENTITY work.dp_hold_ctrl
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  PORT MAP (
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    rst      => rst,
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    clk      => clk,
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    ready    => src_in.ready,
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    in_ctrl  => snk_in.eop,
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    hld_ctrl => hold_in.eop
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  );
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  p_pend_src_out : PROCESS(snk_in, src_out_reg, hold_in)
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  BEGIN
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    -- Pend data
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    IF snk_in.valid='1' THEN
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      i_pend_src_out <= snk_in;       -- Input data
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    ELSE
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      i_pend_src_out <= src_out_reg;  -- Hold data
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    END IF;
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    i_pend_src_out.valid <= snk_in.valid OR hold_in.valid;
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    i_pend_src_out.sync  <= snk_in.sync  OR hold_in.sync;
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    i_pend_src_out.sop   <= snk_in.sop   OR hold_in.sop;
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    i_pend_src_out.eop   <= snk_in.eop   OR hold_in.eop;
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  END PROCESS;
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  p_next_src_out : PROCESS(i_pend_src_out, src_in)
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  BEGIN
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    -- Next data
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    next_src_out       <= i_pend_src_out;
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    -- Next control
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    next_src_out.valid <= i_pend_src_out.valid AND src_in.ready;
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    next_src_out.sync  <= i_pend_src_out.sync  AND src_in.ready;
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    next_src_out.sop   <= i_pend_src_out.sop   AND src_in.ready;
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    next_src_out.eop   <= i_pend_src_out.eop   AND src_in.ready;
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  END PROCESS;
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END rtl;

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