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-------------------------------------------------------------------------------
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--
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danv |
-- Copyright 2020
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danv |
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
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-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
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danv |
--
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-- Licensed under the Apache License, Version 2.0 (the "License");
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-- you may not use this file except in compliance with the License.
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-- You may obtain a copy of the License at
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--
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-- http://www.apache.org/licenses/LICENSE-2.0
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--
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-- Unless required by applicable law or agreed to in writing, software
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-- distributed under the License is distributed on an "AS IS" BASIS,
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-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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-- See the License for the specific language governing permissions and
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-- limitations under the License.
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--
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-------------------------------------------------------------------------------
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LIBRARY IEEE, common_pkg_lib, dp_pkg_lib;
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USE IEEE.std_logic_1164.ALL;
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USE IEEE.numeric_std.ALL;
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USE common_pkg_lib.common_pkg.ALL;
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USE dp_pkg_lib.dp_stream_pkg.ALL;
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-- Purpose:
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-- Adapt the g_in_latency input ready to the g_out_latency output latency.
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-- A typical application is to use this latency adapter to provide a read
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-- ahead interface to a default FIFO with e.g. read latency 1 or 2.
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-- Description:
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-- If g_in_latency > g_out_latency then the input latency is first adapted
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-- to zero latency by means of a latency FIFO. After that a delay line for
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-- src_in.ready yields the g_out_latency output latency.
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-- If g_in_latency < g_out_latency, then a delay line for src_in.ready yields
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-- the g_out_latency output latency.
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-- The sync input is also passed on, only if it occurs during valid. The
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-- constant c_pass_sync_during_not_valid is defined to preserve the
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-- corresponding section of code for passing the sync also during not valid.
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-- Remark:
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-- . The snk_out.ready is derived combinatorially from the src_in.ready. If for
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-- timing performance it is needed to register snk_out.ready, then this can
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-- be done by first increasing the ready latency using this adapter with
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-- g_in_latency = g_out_latency + 1, followed by a second adapter to reach
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-- the required output ready latency latency.
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ENTITY dp_latency_adapter IS
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GENERIC (
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g_in_latency : NATURAL := 3;
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g_out_latency : NATURAL := 1
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);
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PORT (
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rst : IN STD_LOGIC;
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clk : IN STD_LOGIC;
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-- Monitor internal FIFO filling
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fifo_usedw : OUT STD_LOGIC_VECTOR(ceil_log2(2+g_in_latency)-1 DOWNTO 0); -- see description of c_fifo_size, c_usedw_w for explanation of why +2
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fifo_ful : OUT STD_LOGIC;
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fifo_emp : OUT STD_LOGIC;
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-- ST sink
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snk_out : OUT t_dp_siso;
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snk_in : IN t_dp_sosi;
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-- ST source
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src_in : IN t_dp_siso;
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src_out : OUT t_dp_sosi
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);
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END dp_latency_adapter;
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ARCHITECTURE rtl OF dp_latency_adapter IS
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-- The difference between the input ready latency and the output ready latency
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CONSTANT c_diff_latency : INTEGER := g_out_latency - g_in_latency;
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-- Define constant to preserve the corresponding section of code, but default keep it at FALSE
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CONSTANT c_pass_sync_during_not_valid : BOOLEAN := FALSE;
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-- Use g_in_latency+1 words for the FIFO data array, to go to zero latency
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CONSTANT c_high : NATURAL := g_in_latency;
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CONSTANT c_fifo_size : NATURAL := g_in_latency+1; -- +1 because RL=0 also requires a word
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CONSTANT c_usedw_w : NATURAL := ceil_log2(c_fifo_size+1); -- +1 because to store value 2**n requires n+1 bits
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SIGNAL fifo_reg : t_dp_sosi_arr(c_high DOWNTO 0);
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SIGNAL nxt_fifo_reg : t_dp_sosi_arr(c_high DOWNTO 0);
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SIGNAL fifo_reg_valid : STD_LOGIC_VECTOR(c_high DOWNTO 0); -- debug signal for Wave window
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SIGNAL nxt_fifo_usedw : STD_LOGIC_VECTOR(c_usedw_w-1 DOWNTO 0);
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SIGNAL nxt_fifo_ful : STD_LOGIC;
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SIGNAL nxt_fifo_emp : STD_LOGIC;
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SIGNAL ff_siso : t_dp_siso; -- SISO ready
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SIGNAL ff_sosi : t_dp_sosi; -- SOSI
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SIGNAL i_snk_out : t_dp_siso := c_dp_siso_rdy;
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BEGIN
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-- Use i_snk_out with defaults to force unused snk_out bits and fields to '0'
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snk_out <= i_snk_out;
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gen_wires : IF c_diff_latency = 0 GENERATE -- g_out_latency = g_in_latency
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i_snk_out <= src_in; -- SISO
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src_out <= snk_in; -- SOSI
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END GENERATE gen_wires;
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no_fifo : IF c_diff_latency > 0 GENERATE -- g_out_latency > g_in_latency
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-- Go from g_in_latency to required larger g_out_latency
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u_latency : ENTITY work.dp_latency_increase
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GENERIC MAP (
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g_in_latency => g_in_latency,
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g_incr_latency => c_diff_latency
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)
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PORT MAP (
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rst => rst,
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clk => clk,
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-- ST sink
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snk_out => i_snk_out,
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snk_in => snk_in,
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-- ST source
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src_in => src_in,
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src_out => src_out
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);
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END GENERATE no_fifo;
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gen_fifo : IF c_diff_latency < 0 GENERATE -- g_out_latency < g_in_latency
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-- Register [0] contains the FIFO output with zero ready latency
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ff_sosi <= fifo_reg(0);
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p_clk_fifo : PROCESS(rst, clk)
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BEGIN
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IF rst='1' THEN
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fifo_reg <= (OTHERS=>c_dp_sosi_rst);
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fifo_usedw <= (OTHERS=>'0');
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fifo_ful <= '0';
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fifo_emp <= '1';
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ELSIF rising_edge(clk) THEN
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fifo_reg <= nxt_fifo_reg;
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fifo_usedw <= nxt_fifo_usedw;
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fifo_ful <= nxt_fifo_ful;
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fifo_emp <= nxt_fifo_emp;
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END IF;
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END PROCESS;
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-- Pass on frame level flow control
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i_snk_out.xon <= src_in.xon;
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p_snk_out_ready : PROCESS(fifo_reg, ff_siso, snk_in)
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BEGIN
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i_snk_out.ready <= '0';
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IF ff_siso.ready='1' THEN
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-- Default snk_out ready when the source is ready.
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i_snk_out.ready <= '1';
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ELSE
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-- Extra snk_out ready to look ahead for src_in RL = 0.
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-- The fifo_reg[h:0] size is g_in_latency+1 number of SOSI values.
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-- . The fifo_reg[h:1] provide free space for h=g_in_latency nof data
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-- when snk_out.ready is pulled low, because then there can still
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-- arrive g_in_latency nof new data with snk_in.valid asserted.
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-- . The [0] is the registered output SOSI value with RL=0. Therefore
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-- fifo_reg[0] can still accept a new input when ff_siso.ready is
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-- low. If this assignment is omitted then the functionallity is
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-- still OK, but the throughtput sligthly reduces.
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IF fifo_reg(0).valid='0' THEN
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i_snk_out.ready <= '1';
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ELSIF fifo_reg(1).valid='0' THEN
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i_snk_out.ready <= NOT(snk_in.valid);
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END IF;
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END IF;
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END PROCESS;
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p_fifo_reg : PROCESS(fifo_reg, ff_siso, snk_in)
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BEGIN
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-- Keep or shift the fifo_reg dependent on ff_siso.ready, no need to explicitly check fifo_reg().valid
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nxt_fifo_reg <= fifo_reg;
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IF ff_siso.ready='1' THEN
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nxt_fifo_reg(c_high-1 DOWNTO 0) <= fifo_reg(c_high DOWNTO 1);
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nxt_fifo_reg(c_high).valid <= '0';
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nxt_fifo_reg(c_high).sync <= '0';
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nxt_fifo_reg(c_high).sop <= '0';
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nxt_fifo_reg(c_high).eop <= '0';
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-- Forcing the nxt_fifo_reg[h] control fields to '0' is robust, but not
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-- strictly necessary, because the control fields in fifo_reg[h] will
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-- have been set to '0' already earlier due to the snk_in when
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-- ff_siso.ready was '0'.
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END IF;
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-- Put input data at the first available location dependent on ff_siso.ready, no need to explicitly check snk_in.valid
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IF fifo_reg(0).valid='0' THEN
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nxt_fifo_reg(0) <= snk_in; -- fifo_reg is empty
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ELSE
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-- The fifo_reg is not empty, so filled to some extend
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FOR I IN 1 TO c_high LOOP
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IF fifo_reg(I).valid='0' THEN
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IF ff_siso.ready='0' THEN
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nxt_fifo_reg(I) <= snk_in;
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ELSE
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nxt_fifo_reg(I-1) <= snk_in;
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END IF;
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EXIT;
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END IF;
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END LOOP;
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-- Default the input sync during input data valid is only passed on with the valid input data.
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-- When c_pass_sync_during_not_valid is enabled then the input sync during input data not valid is passed on via the head fifo_reg(0) if the fifo_reg is empty.
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IF c_pass_sync_during_not_valid=TRUE AND snk_in.sync='1' AND snk_in.valid='0' THEN
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-- Otherwise for input sync during input data not valid we need to insert the input sync at the last location with valid data independent of ff_siso.ready, to avoid that it gets lost.
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-- For streams that do not use the sync this logic will be void and optimize away by synthesis, because then snk_in.sync = '0' fixed.
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IF fifo_reg(c_high).valid='1' THEN -- fifo_reg is full
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nxt_fifo_reg(c_high).sync <= '1'; -- insert input sync
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ELSE
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FOR I IN c_high-1 DOWNTO 0 LOOP -- fifo_reg is filled to some extend, so not full and not empty
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IF fifo_reg(I).valid='1' THEN
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nxt_fifo_reg(I+1).sync <= '0'; -- overrule default sync assignment
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nxt_fifo_reg(I).sync <= '1'; -- insert input sync
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EXIT;
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END IF;
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END LOOP;
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END IF;
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END IF;
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END IF;
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END PROCESS;
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p_fifo_usedw : PROCESS(nxt_fifo_reg)
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BEGIN
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nxt_fifo_usedw <= (OTHERS=>'0');
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FOR I IN c_high DOWNTO 0 LOOP
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IF nxt_fifo_reg(I).valid='1' THEN
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nxt_fifo_usedw <= TO_UVEC(I+1, c_usedw_w);
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EXIT;
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END IF;
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END LOOP;
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END PROCESS;
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fifo_reg_valid <= func_dp_stream_arr_get(fifo_reg, "VALID");
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nxt_fifo_ful <= '1' WHEN TO_UINT(nxt_fifo_usedw)>=c_high+1 ELSE '0'; -- using >= or = is equivalent here
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nxt_fifo_emp <= '1' WHEN TO_UINT(nxt_fifo_usedw) =0 ELSE '0';
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-- Go from 0 FIFO latency to required g_out_latency (only wires when g_out_latency=0)
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u_latency : ENTITY work.dp_latency_increase
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GENERIC MAP (
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g_in_latency => 0,
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g_incr_latency => g_out_latency
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)
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PORT MAP (
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rst => rst,
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clk => clk,
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-- ST sink
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snk_out => ff_siso,
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snk_in => ff_sosi,
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-- ST source
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src_in => src_in,
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src_out => src_out
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);
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END GENERATE gen_fifo;
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END rtl;
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