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[/] [dp_components/] [trunk/] [dp_xonoff.vhd] - Blame information for rev 4

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-------------------------------------------------------------------------------
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--
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-- Copyright 2020
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-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
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-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
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-- 
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-- Licensed under the Apache License, Version 2.0 (the "License");
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-- you may not use this file except in compliance with the License.
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-- You may obtain a copy of the License at
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-- 
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--     http://www.apache.org/licenses/LICENSE-2.0
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-- 
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-- Unless required by applicable law or agreed to in writing, software
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-- distributed under the License is distributed on an "AS IS" BASIS,
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-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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-- See the License for the specific language governing permissions and
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-- limitations under the License.
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--
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-------------------------------------------------------------------------------
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-- Purpose: Add flow XON-XOFF control by flushing frames
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-- Description:
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-- . The in_siso.ready = out_siso.ready so passed on unchanged, to support
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--   detailed output to input flow control per cycle. The in_siso.xon is
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--   always '1', because the out_siso.xon is taken care of in this
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--   dp_xonoff.vhd by flushing any in_sosi data when out_siso.xon = '0'.
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--
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-- . When g_bypass=TRUE then the in and out are wired and the component is void.
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-- . When g_bypass=FALSE then:
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--     The output is ON when flush='0'.
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--     The output is OFF when flush='1'.
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--     The transition from OFF to ON occurs after an in_sosi.eop so between frames
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--     The transition from ON to OFF occurs after an in_sosi.eop so between frames
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--     Thanks to frm_busy it is also possible to switch between frames, so it
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--     is not necessary that first an eop occurs, before the xon can change. 
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--     The possibility to switch xon at an eop is needed to be able to switch
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--     xon in case there are no gaps between the frames.
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-- . The primary control is via out_siso.xon, however there is an option to override
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--   the out_siso.xon control and force the output to off by using force_xoff.
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-- Remark:
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-- . The output controls are not registered.
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-- . The xon timing is not cycle critical therefor register flush to ease
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--   timing closure
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-- . Originally based on rad_frame_onoff from LOFAR RSP firmware
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LIBRARY IEEE, dp_pkg_lib;
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USE IEEE.std_logic_1164.ALL;
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USE dp_pkg_lib.dp_stream_pkg.ALL;
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ENTITY dp_xonoff IS
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  GENERIC (
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    g_bypass : BOOLEAN := FALSE
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  );
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  PORT (
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    rst           : IN  STD_LOGIC;
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    clk           : IN  STD_LOGIC;
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    -- Frame in
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    in_siso       : OUT t_dp_siso;
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    in_sosi       : IN  t_dp_sosi;
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    -- Frame out
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    out_siso      : IN  t_dp_siso;  -- flush control via out_siso.xon
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    out_sosi      : OUT t_dp_sosi;
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    -- Optional override to force XOFF ('1' = enable override)
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    force_xoff    : IN  STD_LOGIC := '0'
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  );
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END dp_xonoff;
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ARCHITECTURE rtl OF dp_xonoff IS
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  SIGNAL frm_busy     : STD_LOGIC;
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  SIGNAL frm_busy_reg : STD_LOGIC;
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  SIGNAL flush      : STD_LOGIC;
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  SIGNAL nxt_flush  : STD_LOGIC;
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  SIGNAL out_en     : STD_LOGIC;
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  SIGNAL nxt_out_en : STD_LOGIC;
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BEGIN
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  gen_bypass : IF g_bypass=TRUE GENERATE
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    in_siso  <= out_siso;
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    out_sosi <= in_sosi;
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  END GENERATE;
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  no_bypass : IF g_bypass=FALSE GENERATE
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    in_siso.ready <= out_siso.ready;  -- pass on ready for detailed flow control per cycle
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    in_siso.xon <= '1';               -- upstream can remain on, because flush will handle out_siso.xon
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    nxt_flush <= NOT out_siso.xon OR force_xoff; -- use xon for flow control at frame level
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    p_clk: PROCESS(clk, rst)
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    BEGIN
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      IF rst='1' THEN
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        frm_busy_reg <= '0';
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        flush        <= '0';
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        out_en       <= '1';
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      ELSIF rising_edge(clk) THEN
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        frm_busy_reg <= frm_busy;
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        flush        <= nxt_flush;     -- pipeline register flush to ease timing closure
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        out_en       <= nxt_out_en;    -- state register out_en because it can only change between frames
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      END IF;
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    END PROCESS;
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    -- Detect in_sosi frame busy, frm_busy is '1' from sop including sop, until eop excluding eop
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    p_frm_busy : PROCESS(in_sosi, in_sosi, frm_busy_reg)
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    BEGIN
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      frm_busy <= frm_busy_reg;
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      IF in_sosi.sop='1' THEN
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        frm_busy <= '1';
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      ELSIF in_sosi.eop='1' THEN
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        frm_busy <= '0';
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      END IF;
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    END PROCESS;
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    p_out_en : PROCESS(flush, out_en, frm_busy)
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    BEGIN
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      nxt_out_en <= out_en;
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      IF frm_busy='0' THEN
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        IF flush='1' THEN
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          nxt_out_en <= '0';
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        ELSE
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          nxt_out_en <= '1';
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        END IF;
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      END IF;
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    END PROCESS;
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    p_out_sosi : PROCESS(in_sosi, out_en)
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    BEGIN
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      -- Pass on sosi data via wires
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      out_sosi       <= in_sosi;
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      -- XON/XOFF flow control via sosi control
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      out_sosi.sync  <= in_sosi.sync  AND out_en;
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      out_sosi.valid <= in_sosi.valid AND out_en;
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      out_sosi.sop   <= in_sosi.sop   AND out_en;
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      out_sosi.eop   <= in_sosi.eop   AND out_en;
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    END PROCESS;
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  END GENERATE;
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END ARCHITECTURE;

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