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-------------------------------------------------------------------------------
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--
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danv |
-- Copyright 2020
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danv |
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
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-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
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danv |
--
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-- Licensed under the Apache License, Version 2.0 (the "License");
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-- you may not use this file except in compliance with the License.
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-- You may obtain a copy of the License at
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--
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-- http://www.apache.org/licenses/LICENSE-2.0
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--
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-- Unless required by applicable law or agreed to in writing, software
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-- distributed under the License is distributed on an "AS IS" BASIS,
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-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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-- See the License for the specific language governing permissions and
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-- limitations under the License.
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danv |
--
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-------------------------------------------------------------------------------
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LIBRARY IEEE, common_pkg_lib, dp_pkg_lib;
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USE IEEE.std_logic_1164.ALL;
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USE IEEE.numeric_std.ALL;
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USE common_pkg_lib.common_pkg.ALL;
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USE dp_pkg_lib.dp_stream_pkg.ALL;
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USE dp_pkg_lib.tb_dp_pkg.ALL;
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ENTITY tb_dp_latency_adapter IS
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END tb_dp_latency_adapter;
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ARCHITECTURE tb OF tb_dp_latency_adapter IS
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-- See tb_dp_pkg.vhd for explanation and run time
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SUBTYPE t_dut_range IS INTEGER RANGE -1 to INTEGER'HIGH;
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TYPE t_dut_natural_arr IS ARRAY (t_dut_range RANGE <>) OF NATURAL;
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TYPE t_dut_data_arr IS ARRAY (t_dut_range RANGE <>) OF STD_LOGIC_VECTOR(c_dp_data_w-1 DOWNTO 0);
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TYPE t_dut_logic_arr IS ARRAY (t_dut_range RANGE <>) OF STD_LOGIC; -- can not use STD_LOGIC_VECTOR because of integer range
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-- TX ready latency to DUT chain
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CONSTANT c_tx_latency : NATURAL := 3;
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CONSTANT c_tx_void : NATURAL := sel_a_b(c_tx_latency, 1, 0); -- used to avoid empty range VHDL warnings when c_tx_latency=0
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CONSTANT c_tx_offset_sop : NATURAL := 3;
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CONSTANT c_tx_period_sop : NATURAL := 7; -- sop in data valid cycle 3, 10, 17, ...
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CONSTANT c_tx_offset_eop : NATURAL := 5; -- eop in data valid cycle 5, 12, 19, ...
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CONSTANT c_tx_period_eop : NATURAL := c_tx_period_sop;
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CONSTANT c_tx_offset_sync : NATURAL := 3; -- sync in data valid cycle 3, 20, 37, ...
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CONSTANT c_tx_period_sync : NATURAL := 17;
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-- The TB supports using 1 or more dp_latency_adapter Devices Under Test in a chain. DUT 0 is the first DUT and it
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-- gets the tx_data from this test bench, which has index -1. Each next DUT gets its input from the previous DUT,
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-- hence the ready latency between DUTs should be the same.
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-- The output latency of the previous must equal the input latency of the next DUT, hence it is sufficient to define
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-- only the DUT output latencies.
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--CONSTANT c_dut_latency : t_dut_natural_arr := (c_tx_latency, 3); -- verify single dp_latency_adapter with only wires
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--CONSTANT c_dut_latency : t_dut_natural_arr := (c_tx_latency, 4); -- verify single dp_latency_adapter with latency increase
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--CONSTANT c_dut_latency : t_dut_natural_arr := (c_tx_latency, 1); -- verify single dp_latency_adapter with latency decrease
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CONSTANT c_dut_latency : t_dut_natural_arr := (c_tx_latency, 1, 2, 0, 5, 5, 2, 1, 0, 7);
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-- The nof dut latencies in the c_dut_latency array automatically also defines the nof DUTs c_nof_dut.
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CONSTANT c_nof_dut : NATURAL := c_dut_latency'HIGH+1;
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-- RX ready latency from DUT chain
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CONSTANT c_rx_latency : NATURAL := c_dut_latency(c_nof_dut-1);
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CONSTANT c_verify_en_wait : NATURAL := 10+c_nof_dut*2; -- wait some cycles before asserting verify enable
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CONSTANT c_empty_offset : NATURAL := 1;
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CONSTANT c_channel_offset : NATURAL := 2;
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CONSTANT c_random_w : NATURAL := 19;
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SIGNAL tb_end : STD_LOGIC := '0';
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SIGNAL clk : STD_LOGIC := '0';
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SIGNAL rst : STD_LOGIC;
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SIGNAL sync : STD_LOGIC;
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SIGNAL lfsr1 : STD_LOGIC_VECTOR(c_random_w-1 DOWNTO 0) := (OTHERS=>'0');
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SIGNAL lfsr2 : STD_LOGIC_VECTOR(c_random_w DOWNTO 0) := (OTHERS=>'0');
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SIGNAL cnt_dat : STD_LOGIC_VECTOR(c_dp_data_w-1 DOWNTO 0);
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SIGNAL cnt_val : STD_LOGIC;
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SIGNAL cnt_en : STD_LOGIC;
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SIGNAL tx_data : t_dp_data_arr(0 TO c_tx_latency + c_tx_void);
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SIGNAL tx_val : STD_LOGIC_VECTOR(0 TO c_tx_latency + c_tx_void);
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SIGNAL in_ready : STD_LOGIC;
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SIGNAL in_data : STD_LOGIC_VECTOR(c_dp_data_w-1 DOWNTO 0);
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SIGNAL in_sync : STD_LOGIC;
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SIGNAL in_val : STD_LOGIC;
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SIGNAL in_sop : STD_LOGIC;
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SIGNAL in_eop : STD_LOGIC;
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-- DUT index -1 = in_data
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SIGNAL dut_ready : t_dut_logic_arr(-1 TO c_nof_dut-1); -- SISO
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SIGNAL dut_data : t_dut_data_arr(-1 TO c_nof_dut-1); -- SOSI
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SIGNAL dut_empty : t_dut_data_arr(-1 TO c_nof_dut-1) := (OTHERS=>(OTHERS=>'0'));
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SIGNAL dut_channel : t_dut_data_arr(-1 TO c_nof_dut-1) := (OTHERS=>(OTHERS=>'0'));
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SIGNAL dut_sync : t_dut_logic_arr(-1 TO c_nof_dut-1);
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SIGNAL dut_val : t_dut_logic_arr(-1 TO c_nof_dut-1);
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SIGNAL dut_sop : t_dut_logic_arr(-1 TO c_nof_dut-1);
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SIGNAL dut_eop : t_dut_logic_arr(-1 TO c_nof_dut-1);
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-- DUT index c_nof_dut-1 = out_data
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SIGNAL dut_siso : t_dp_siso_arr(-1 TO c_nof_dut-1);
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SIGNAL dut_sosi : t_dp_sosi_arr(-1 TO c_nof_dut-1) := (OTHERS=>c_dp_sosi_rst);
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SIGNAL out_ready : STD_LOGIC;
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SIGNAL prev_out_ready : STD_LOGIC_VECTOR(0 TO c_rx_latency);
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SIGNAL out_data : STD_LOGIC_VECTOR(c_dp_data_w-1 DOWNTO 0);
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SIGNAL out_empty : STD_LOGIC_VECTOR(c_dp_data_w-1 DOWNTO 0);
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SIGNAL out_channel : STD_LOGIC_VECTOR(c_dp_data_w-1 DOWNTO 0);
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SIGNAL out_sync : STD_LOGIC;
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SIGNAL out_val : STD_LOGIC;
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SIGNAL out_sop : STD_LOGIC;
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SIGNAL out_eop : STD_LOGIC;
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SIGNAL hold_out_sop : STD_LOGIC;
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SIGNAL prev_out_data : STD_LOGIC_VECTOR(out_data'RANGE);
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SIGNAL state : t_dp_state_enum;
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SIGNAL verify_en : STD_LOGIC;
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SIGNAL verify_done : STD_LOGIC;
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SIGNAL exp_data : STD_LOGIC_VECTOR(c_dp_data_w-1 DOWNTO 0) := TO_UVEC(19555, c_dp_data_w);
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BEGIN
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-- Use intervals marked by sync to start a new test named by state.
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--
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-- Under all circumstances the out_data should not mis or duplicate a count
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-- while out_val is asserted as checked by p_verify.
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-- The throughput must remain 100%, with only some increase in latency. This
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-- can be checked manually by checking that cnt_val does not toggle when the
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-- out_ready is asserted continuously. E.g. check that the out_data value
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-- is sufficiently high given the number of sync intervals that have passed.
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--
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-- Stimuli to verify the dp_latency_adapter DUT:
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--
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-- * Use various ready latency combinations in c_dut_latency:
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-- . c_in_latency > c_out_latency = 0
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-- . c_in_latency > c_out_latency > 0
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-- . c_in_latency = c_out_latency = 0
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-- . c_in_latency = c_out_latency > 0
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-- . 0 = c_in_latency < c_out_latency
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-- . 0 < c_in_latency < c_out_latency
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--
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-- * Manipulate the stimuli in:
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-- . p_cnt_en : cnt_en not always active when in_ready is asserted
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-- . p_out_ready : out_ready not always active
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clk <= NOT clk OR tb_end AFTER clk_period/2;
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rst <= '1', '0' AFTER clk_period*7;
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-- Sync interval
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proc_dp_sync_interval(clk, sync);
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-- Input data
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cnt_val <= in_ready AND cnt_en;
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proc_dp_cnt_dat(rst, clk, cnt_val, cnt_dat);
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proc_dp_tx_data(c_tx_latency, rst, clk, cnt_val, cnt_dat, tx_data, tx_val, in_data, in_val);
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proc_dp_tx_ctrl(c_tx_offset_sync, c_tx_period_sync, in_data, in_val, in_sync);
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proc_dp_tx_ctrl(c_tx_offset_sop, c_tx_period_sop, in_data, in_val, in_sop);
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proc_dp_tx_ctrl(c_tx_offset_eop, c_tx_period_eop, in_data, in_val, in_eop);
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-- Stimuli control
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proc_dp_count_en(rst, clk, sync, lfsr1, state, verify_done, tb_end, cnt_en);
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proc_dp_out_ready(rst, clk, sync, lfsr2, out_ready);
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-- Output verify
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proc_dp_verify_en(c_verify_en_wait, rst, clk, sync, verify_en);
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proc_dp_verify_data("out_data", c_rx_latency, clk, verify_en, out_ready, out_val, out_data, prev_out_data);
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proc_dp_verify_valid(c_rx_latency, clk, verify_en, out_ready, prev_out_ready, out_val);
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proc_dp_verify_ctrl(c_tx_offset_sync, c_tx_period_sync, "sync", clk, verify_en, out_data, out_val, out_sync);
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proc_dp_verify_ctrl(c_tx_offset_sop, c_tx_period_sop, "sop", clk, verify_en, out_data, out_val, out_sop);
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proc_dp_verify_ctrl(c_tx_offset_eop, c_tx_period_eop, "eop", clk, verify_en, out_data, out_val, out_eop);
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proc_dp_verify_sop_and_eop(c_rx_latency, FALSE, clk, out_val, out_val, out_sop, out_eop, hold_out_sop); -- Verify that sop and eop come in pairs, no check on valid between eop and sop
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proc_dp_verify_other_sosi("empty", INCR_UVEC(out_data, c_empty_offset), clk, verify_en, out_empty);
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proc_dp_verify_other_sosi("channel", INCR_UVEC(out_data, c_channel_offset), clk, verify_en, out_channel);
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-- Check that the test has ran at all
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proc_dp_verify_value(e_equal, clk, verify_done, exp_data, out_data);
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------------------------------------------------------------------------------
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-- Chain of 1 or more dp_latency_adapter DUTs
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--
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-- . Note this also models a series of streaming modules in a data path
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--
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------------------------------------------------------------------------------
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-- Map the test bench tx counter data to the input of the chain
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in_ready <= dut_ready(-1);
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dut_data(-1) <= in_data;
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dut_empty(-1) <= INCR_UVEC(in_data, c_empty_offset);
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dut_channel(-1) <= INCR_UVEC(in_data, c_channel_offset);
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dut_sync(-1) <= in_sync;
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dut_val(-1) <= in_val;
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dut_sop(-1) <= in_sop;
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dut_eop(-1) <= in_eop;
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-- map sl, slv to record
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dut_ready(-1) <= dut_siso(-1).ready; -- SISO
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dut_sosi(-1).data(c_dp_data_w-1 DOWNTO 0) <= dut_data(-1); -- SOSI
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dut_sosi(-1).empty <= dut_empty(-1)(c_dp_empty_w-1 DOWNTO 0);
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dut_sosi(-1).channel <= dut_channel(-1)(c_dp_channel_w-1 DOWNTO 0);
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dut_sosi(-1).sync <= dut_sync(-1);
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dut_sosi(-1).valid <= dut_val(-1);
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dut_sosi(-1).sop <= dut_sop(-1);
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dut_sosi(-1).eop <= dut_eop(-1);
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gen_chain : FOR I IN 0 TO c_nof_dut-1 GENERATE
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dut : ENTITY work.dp_latency_adapter
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GENERIC MAP (
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g_in_latency => c_dut_latency(I-1),
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g_out_latency => c_dut_latency(I)
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)
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PORT MAP (
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rst => rst,
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clk => clk,
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-- ST sink
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snk_out => dut_siso(I-1),
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snk_in => dut_sosi(I-1),
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-- ST source
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src_in => dut_siso(I),
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src_out => dut_sosi(I)
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);
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END GENERATE;
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-- map record to sl, slv
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dut_siso(c_nof_dut-1).ready <= dut_ready(c_nof_dut-1); -- SISO
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dut_data(c_nof_dut-1) <= dut_sosi(c_nof_dut-1).data(c_dp_data_w-1 DOWNTO 0); -- SOSI
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dut_empty(c_nof_dut-1)(c_dp_empty_w-1 DOWNTO 0) <= dut_sosi(c_nof_dut-1).empty;
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dut_channel(c_nof_dut-1)(c_dp_channel_w-1 DOWNTO 0) <= dut_sosi(c_nof_dut-1).channel;
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dut_sync(c_nof_dut-1) <= dut_sosi(c_nof_dut-1).sync;
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dut_val(c_nof_dut-1) <= dut_sosi(c_nof_dut-1).valid;
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dut_sop(c_nof_dut-1) <= dut_sosi(c_nof_dut-1).sop;
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dut_eop(c_nof_dut-1) <= dut_sosi(c_nof_dut-1).eop;
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-- Map the output of the DUT chain to the test bench output data
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dut_ready(c_nof_dut-1) <= out_ready;
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out_data <= dut_data(c_nof_dut-1);
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out_empty <= dut_empty(c_nof_dut-1);
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out_channel <= dut_channel(c_nof_dut-1);
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out_sync <= dut_sync(c_nof_dut-1);
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out_val <= dut_val(c_nof_dut-1);
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out_sop <= dut_sop(c_nof_dut-1);
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out_eop <= dut_eop(c_nof_dut-1);
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END tb;
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