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dmsu |
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/* random-walk filter with variable reset */
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module variableresetrandomwalkfilter(MainClock, Lead, Lag, Positive, Negative);
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input MainClock, Lead, Lag; // System Clock and Phase Comparator signals
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output Positive, Negative; // "positive shift" and "negative shift" outputs
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parameter N_FilterLength = 8;
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parameter N_FilterResetValue = 8;
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parameter N_FilterMaxValue = N_FilterResetValue;
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/* 256=2_PWR_8(counter length). Use this value because unsigned arithmetic */
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parameter N_FilterMinValue = 256 - N_FilterResetValue;
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/* the counter length of reset scheme must be short */
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parameter ResetterCounterLength = 4;
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parameter ResetterCounterMaxValue = 3;
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/* 16=2_PWR_4 */
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parameter ResetterCounterMinValue = 16 - 3;
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/* counter "N - RandomWalkFilter" */
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reg [N_FilterLength-1 : 0] N_FilterCounter;
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/* connections of "M - RandomWalkFilter" */
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wire Up, Down;
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randomwalkfilter inst_M_Filter(.MainClock(MainClock), .Lead(Lead), .Lag(Lag),
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.Positive(Up), .Negative(Down));
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defparam inst_M_Filter.FilterResetValue = 32; // length "M-RWF" = 32
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/* Reset Scheme. This counter changes on "M-RWF" counter */
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reg [ResetterCounterLength-1 : 0] ResetterCounter;
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always @(posedge MainClock)
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begin
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if(Up)
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begin
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if((ResetterCounter < ResetterCounterMaxValue) || (ResetterCounter >= ResetterCounterMinValue))
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ResetterCounter <= ResetterCounter + 1;
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end
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else if(Down)
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begin
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if((ResetterCounter <= ResetterCounterMaxValue) || (ResetterCounter > ResetterCounterMinValue))
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ResetterCounter <= ResetterCounter - 1;
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end
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if((ResetterCounter > ResetterCounterMaxValue) && (ResetterCounter < ResetterCounterMinValue))
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ResetterCounter <= 0;
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end
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/* Look-Up Table between ResetterCounter value and reset state of "N-RWF" */
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reg [N_FilterLength-1 : 0] ResetterValue;
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always @(1)
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begin
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case(ResetterCounter)
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16 - 3: ResetterValue = 256 - 7;
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16 - 2: ResetterValue = 256 - 6;
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16 - 1: ResetterValue = 256 - 4;
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0: ResetterValue = 0;
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1: ResetterValue = 4;
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2: ResetterValue = 6;
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3: ResetterValue = 7;
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default: ResetterValue = 0;
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endcase
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end
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/* "N-RWF" Filter has different reset states */
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/* in accordance ResetterCounter value */
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always @(posedge MainClock)
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begin
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if((N_FilterCounter == N_FilterMaxValue) || (N_FilterCounter == N_FilterMinValue))
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N_FilterCounter <= ResetterValue;
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else
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begin
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if(Lead) N_FilterCounter <= N_FilterCounter + 1;
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if(Lag) N_FilterCounter <= N_FilterCounter - 1;
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end
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end
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/* making "Lead" and "Lag" signals when */
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/* counter reached max or min levels */
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reg Positive, Negative;
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always @(posedge MainClock)
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begin
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Positive <= (N_FilterCounter == N_FilterMaxValue);
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Negative <= (N_FilterCounter == N_FilterMinValue);
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end
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endmodule
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