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fixed_extensions user manual
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==============================
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+-------------------+----------------------------------------------------------+
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| **Title** | fixed_extensions (VHDL fixed-point arithmetic extensions |
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| | package) |
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+-------------------+----------------------------------------------------------+
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| **Author** | Nikolaos Kavvadias 2011, 2012, 2013, 2014 |
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+-------------------+----------------------------------------------------------+
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| **Contact** | nikos@nkavvadias.com |
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+-------------------+----------------------------------------------------------+
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| **Website** | http://www.nkavvadias.com |
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+-------------------+----------------------------------------------------------+
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| **Release Date** | 21 February 2014 |
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+-------------------+----------------------------------------------------------+
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| **Version** | 0.1.0 |
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+-------------------+----------------------------------------------------------+
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| **Rev. history** | |
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+-------------------+----------------------------------------------------------+
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| **v0.1.0** | 21-02-2014 |
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| | |
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| | Changed documentation format to RestructuredText. |
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+-------------------+----------------------------------------------------------+
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| **v0.0.5** | 25-07-2011 |
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| | First public release. |
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+-------------------+----------------------------------------------------------+
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1. Introduction
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===============
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``fixed_extensions_pkg`` is a fixed-point arithmetic package written in VHDL
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according to the VHDL-2008 update of the standard. It uses VHDL-2008 back-
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compatible libraries (by David Bishop) that are included in this distribution
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for the sake of completeness.
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Currently, the "fixed_extensions_pkg" package implements the following:
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-ceil:
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round towards plus infinity.
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-fix:
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round towards zero.
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-floor:
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round towards minus infinity.
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-round:
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round to nearest; ties to greatest absolute value.
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-nearest:
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round to nearest; ties to plus infinity.
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-convergent:
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round to nearest; ties to closest even.
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-bitinsert:
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bit-field insertion to word
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-bitextract:
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bit-field extraction from word
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``fixed_extensions`` is distributed along with a tool (gentestround) to generate
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customized VHDL test designs.
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The ``fixed_extensions`` project can be download from the following OpenCores
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website: http://opencores.org/project,fixed_extensions
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2. File listing
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===============
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The ``fixed_extensions`` distribution includes the following files:
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+-----------------------+------------------------------------------------------+
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| /fixed_extensions | Top-level directory |
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+-----------------------+------------------------------------------------------+
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| /bench/vhdl | Benchmarks VHDL directory |
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+-----------------------+------------------------------------------------------+
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| testrounding_tb.vhd | Standard testbench file. |
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+-----------------------+------------------------------------------------------+
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| /doc | Documentation directory |
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+-----------------------+------------------------------------------------------+
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| AUTHORS | List of authors. |
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+-----------------------+------------------------------------------------------+
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| BUGS | Bug list. |
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+-----------------------+------------------------------------------------------+
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| ChangeLog | A log for code changes. |
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+-----------------------+------------------------------------------------------+
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| COPYING.BSD | The modified BSD license. |
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+-----------------------+------------------------------------------------------+
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| README | This file. |
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+-----------------------+------------------------------------------------------+
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| README.html | HTML version of README. |
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+-----------------------+------------------------------------------------------+
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| README.pdf | PDF version of README. |
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+-----------------------+------------------------------------------------------+
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| rst2docs.sh | Bash script for generating the HTML and PDF versions.|
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+-----------------------+------------------------------------------------------+
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| THANKS | Acknowledgements. |
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+-----------------------+------------------------------------------------------+
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| TODO | A list of future enhancements. |
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+-----------------------+------------------------------------------------------+
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| VERSION | Current version of the project sources. |
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+-----------------------+------------------------------------------------------+
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| /gen/vhdl | Generated RTL VHDL code directory. |
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+-----------------------+------------------------------------------------------+
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| testroundings.vhd | Auto-generated test file for sfixed arithmetic. |
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+-----------------------+------------------------------------------------------+
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| testroundingu.vhd | Auto-generated test file for ufixed arithmetic. |
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+-----------------------+------------------------------------------------------+
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| /rtl/vhdl | RTL source code directory for the package |
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+-----------------------+------------------------------------------------------+
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| fixed_extensions_pkg- | The VHDL package for simulation-oriented use. |
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| _sim.vhd | |
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+-----------------------+------------------------------------------------------+
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| /sim/rtl_sim | RTL simulation files directory |
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+-----------------------+------------------------------------------------------+
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| /sim/rtl_sim/bin | RTL simulation scripts directory |
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+-----------------------+------------------------------------------------------+
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| run.sh | A bash script for testing the package. |
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+-----------------------+------------------------------------------------------+
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| testroundings.do | Modelsim macro script for testing sfixed arithmetic. |
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+-----------------------+------------------------------------------------------+
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| testroundings.sh | Bash script for running an sfixed simulation. |
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+-----------------------+------------------------------------------------------+
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| testroundingu.do | Modelsim macro script for testing ufixed arithmetic. |
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+-----------------------+------------------------------------------------------+
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| testroundingu.sh | Bash script for running an ufixed simulation. |
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+-----------------------+------------------------------------------------------+
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| /sim/rtl_sim/src | Various source files for running RTL simulations |
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+-----------------------+------------------------------------------------------+
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| fixed_float_typ | VHDL package with definitions for fixed-point |
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| es_custom.vhd | arithmetic. |
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+-----------------------+------------------------------------------------------+
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| fixed_pkg_c.vhd | VHDL package implementing fixed-point arithmetic |
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| | (VHDL'93 version of the VHDL-2008 package as found |
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| | http://www.eda.org/fphdl/). |
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+-----------------------+------------------------------------------------------+
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| math_real.vhd | VHDL package with some real arithmetic functions |
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| | (also part of the IEEE 1076 standard for VHDL). |
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+-----------------------+------------------------------------------------------+
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| /sw | Software utilities |
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+-----------------------+------------------------------------------------------+
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| Makefile | Makefile for compiling the test design generator. |
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+-----------------------+------------------------------------------------------+
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| gentestround.c | Test design generator written in ANSI C. |
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+-----------------------+------------------------------------------------------+
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3. ``fixed_extensions`` usage
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=============================
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The fixed_extensions package can be used as follows. Assuming that the user has
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changed directory to ``./fixed_extensions``, the following can be used:
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| ``$ cd sim/rtl_sim/bin``
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| ``$ ./run.sh``
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Alternatively, the user can only generate and run some tests for solely the
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signed fixed-point and unsigned fixed-point data types. This is correspondingly
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performed as:
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| ``$ ./testroundings.sh``
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and
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| ``$./testroundingu.sh``
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4. Prerequisities
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=================
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- Standard UNIX-based tools (tested on cygwin/x86)
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* make
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* bash
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- [optional] Mentor Modelsim (``mti``) from http://www.model.com
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Provides a simulation environment to run the tests.
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