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[/] [fixed_point_arithmetic_parameterized/] [trunk/] [testfixtures/] [qdiv_tf.v] - Blame information for rev 3

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1 3 samis13
`timescale 1ns / 1ps
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////////////////////////////////////////////////////////////////////////////////
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// Company: 
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// Engineer:
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//
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// Create Date:   19:41:28 08/24/2011
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// Design Name:   divider
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// Module Name:   C:/Documents and Settings/samskalicky/Desktop/PLE/divider_tf.v
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// Project Name:  PLE
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// Target Device:  
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// Tool versions:  
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// Description: 
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//
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// Verilog Test Fixture created by ISE for module: divider
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//
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// Dependencies:
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// 
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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// 
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////////////////////////////////////////////////////////////////////////////////
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module qdiv_tf;
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//Parameterized values
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        parameter Q = 15;
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        parameter N = 32;
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        // Inputs
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        reg [N-1:0] dividend;
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        reg [N-1:0] divisor;
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        reg start;
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        reg clk;
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        real top;
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        real bottom;
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        // Outputs
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        wire [N-1:0] quotient;
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        wire done;
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        real result;
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        // Instantiate the Unit Under Test (UUT)
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        //module  Params  Name  Signals
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        qdiv #(Q,N)     uut (dividend, divisor, start, clk, quotient,done);
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        initial begin
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                // Initialize Inputs
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                top = -32.5;
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                bottom = 2.25;
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                conv_rational(top,dividend);
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                conv_rational(bottom,divisor);
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                start = 1;
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                clk = 0;
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                // Wait 100 ns for global reset to finish
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                #100;
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                // Add stimulus here
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                start = 0;
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                #366;
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                conv_fixed(quotient,result);
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                $display("%f / %f = %f",top,bottom,result);
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        end
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        always
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        begin
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                #5 clk = ~clk;
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        end
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        /*
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         *      Task to convert from rational to fixed point
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         */
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         task conv_rational;
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         input real num;
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         output [N-1:0] fixed;
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         integer i;
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         real tmp;
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         begin
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                 tmp = num;
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                 //set sign
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                 if(tmp < 0) begin
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                 //if its negative, set the sign bit and make the temporary number position by multiplying by -1
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                        fixed[N-1] = 1;
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                        tmp = tmp * -1;
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                 end
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                 else begin
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                 //if its positive, the sign bit is zero
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                        fixed[N-1] = 0;
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                 end
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                 //check that the number isnt too large
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                 if(tmp > (1 << N-Q-1)) begin
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                        $display("Error!!! rational number %f is larger than %d whole bits can represent!",num,N-Q-1);
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                 end
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                 //set whole part
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                 for(i=0; i<N-Q-1; i=i+1) begin
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                        if(tmp >= (1 << N-Q-2-i)) begin
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                        //if its greater or equal, subtract out this power of 2 and put a one at this position
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                                fixed[N-2-i] = 1;
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                                tmp = tmp - (1 << N-Q-2-i);
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                        end
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                        else begin
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                        //if its less, put a zero at this position
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                                fixed[N-2-i] = 0;
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                        end
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                 end
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                 //set fractional part
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                 for(i=1; i<=Q; i=i+1) begin
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                        if(tmp >= 1.0/(1 << i)) begin
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                        //if its greater or equal, subtract out this power of 2 and put a one at this position
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                                fixed[Q-i] = 1;
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                                tmp = tmp - 1.0/(1 << i);
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                        end
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                        else begin
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                        //if its less, put a zero at this position
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                                fixed[Q-i] = 0;
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                        end
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                 end
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                 //check that the number isnt too small (loss of precision)
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                 if(tmp > 0) begin
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                        $display("Error!!! LOSS OF PRECISION converting rational number %f's fractional part using %d bits!",num,Q);
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                 end
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         end
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         endtask;
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         /*
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         *      Task to convert from fixed point to rational
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         */
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         task conv_fixed;
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         input [N-1:0] fixed;
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         output real num;
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         integer i;
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         begin
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                 num = 0;
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                 //set whole part
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                 for(i=0; i<N-Q-1; i=i+1) begin
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                        if(fixed[N-2-i] == 1) begin
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                        //if theres a one at this position, add the power of 2 to the rational number
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                                num = num + (1 << N-Q-2-i);
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                        end
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                 end
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                 //set fractional part
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                 for(i=1; i<=Q; i=i+1) begin
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                        if(fixed[Q-i] == 1) begin
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                        //if theres a one at this position, add the power of 2 to the rational number
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                                num = num + 1.0/(1 << i);
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                        end
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                 end
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                 //set sign
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                 if(fixed[N-1] == 1) begin
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                 //if the sign bit is set, negate the rational number
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                        num = num * -1;
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                 end
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         end
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         endtask;
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endmodule

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