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[/] [gpib_controller/] [trunk/] [vhdl/] [src/] [gpib/] [if_func_AH.vhd] - Blame information for rev 13

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1 13 Andrewski
--------------------------------------------------------------------------------
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--This file is part of fpga_gpib_controller.
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--
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-- Fpga_gpib_controller is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- Fpga_gpib_controller is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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-- GNU General Public License for more details.
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-- You should have received a copy of the GNU General Public License
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-- along with Fpga_gpib_controller.  If not, see <http://www.gnu.org/licenses/>.
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----------------------------------------------------------------------------------
17 13 Andrewski
-- Author: Andrzej Paluch
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-- 
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-- Create Date:    01:04:57 10/01/2011 
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-- Design Name: 
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-- Module Name:    if_func_AH - Behavioral 
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-- Project Name: 
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-- Target Devices: 
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-- Tool versions: 
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-- Description: 
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--
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-- Dependencies: 
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--
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-- Revision: 
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-- Revision 0.01 - File Created
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-- Additional Comments: 
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use work.utilPkg.all;
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entity if_func_AH is
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        port(
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                -- device inputs
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                clk : in std_logic; -- clock
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                pon : in std_logic; -- power on
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                rdy : in std_logic; -- ready for next message
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                tcs : in std_logic; -- take control synchronously
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                -- state inputs
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                LACS : in std_logic; -- listener active state
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                LADS : in std_logic; -- listener addressed state
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                -- interface inputs
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                ATN : in std_logic; -- attention
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                DAV : in std_logic; -- data accepted
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                -- interface outputs
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                RFD : out std_logic; -- ready for data
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                DAC : out std_logic; -- data accepted
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                -- reported state
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                ANRS : out std_logic; -- acceptor not ready state
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                ACDS : out std_logic -- accept data state
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        );
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end if_func_AH;
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architecture Behavioral of if_func_AH is
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        -- states
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        type AH_STATE is (
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                -- acceptor idle state
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                ST_AIDS,
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                -- acceptor not ready state
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                ST_ANRS,
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                -- acceptor ready state
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                ST_ACRS,
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                -- acceptor wait for new cycle state
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                ST_AWNS,
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                -- accept data state
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                ST_ACDS
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        );
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        -- current state
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        signal current_state : AH_STATE;
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        -- events
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        signal event1, event2, event3, event4, event5, event6, event7 : boolean;
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        -- timers
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        constant TIMER_T3_MAX : integer := 3;
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        constant TIMER_T3_TIMEOUT : integer := 2;
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        signal timerT3 : integer range 0 to TIMER_T3_MAX;
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        signal timerT3Expired : boolean;
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begin
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        -- state machine process
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        process(pon, clk) begin
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                if pon = '1' then
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                        current_state <= ST_AIDS;
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                elsif rising_edge(clk) then
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                        case current_state is
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                                ------------------
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                                when ST_AIDS =>
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                                        if event2 then
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                                                -- no state change
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                                        elsif event1 then
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                                                current_state <= ST_ANRS;
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                                        end if;
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                                ------------------
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                                when ST_ANRS =>
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                                        if event2 then
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                                                current_state <= ST_AIDS;
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                                        elsif event4 then
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                                                current_state <= ST_ACRS;
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                                        end if;
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                                ------------------
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                                when ST_ACRS =>
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                                        if event2 then
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                                                current_state <= ST_AIDS;
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                                        elsif event5 then
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                                                current_state <= ST_ANRS;
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                                        elsif event6 then
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                                                timerT3 <= 0;
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                                                current_state <= ST_ACDS;
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                                        end if;
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                                ------------------
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                                when ST_ACDS =>
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                                        if event2 then
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                                                current_state <= ST_AIDS;
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                                        elsif event3 then
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                                                current_state <= ST_AWNS;
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                                        end if;
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                                        if timerT3 < TIMER_T3_MAX then
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                                                timerT3 <= timerT3 + 1;
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                                        end if;
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                                ------------------
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                                when ST_AWNS =>
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                                        if event2 then
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                                                current_state <= ST_AIDS;
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                                        elsif event7 then
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                                                current_state <= ST_ANRS;
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                                        end if;
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                                ------------------
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                                when others =>
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                                        current_state <= ST_AIDS;
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                        end case;
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                end if;
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        end process;
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        -- events
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        event1 <= ATN='1' or LACS='1' or LADS='1';
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        event2 <= not(ATN='1' or LACS='1' or LADS='1');
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        event3 <= (rdy='0' and ATN='0') or (timerT3Expired and ATN='1');
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        event4 <= (ATN='1' or rdy='1') and tcs='0';
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        event5 <= not (ATN='1' or rdy='1');
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        event6 <= DAV = '1';
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        event7 <= DAV = '0';
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        -- timers
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        timerT3Expired <= timerT3 >= TIMER_T3_TIMEOUT;
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        RFD <= to_stdl(
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                        current_state = ST_AIDS or
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                        current_state = ST_ACRS
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                );
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        DAC <= to_stdl(
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                        current_state = ST_AIDS or
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                        current_state = ST_AWNS
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                );
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        ACDS <= to_stdl(current_state = ST_ACDS);
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        ANRS <= to_stdl(current_state = ST_ANRS);
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end Behavioral;
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