OpenCores
URL https://opencores.org/ocsvn/gpib_controller/gpib_controller/trunk

Subversion Repositories gpib_controller

[/] [gpib_controller/] [trunk/] [vhdl/] [src/] [gpib_helper/] [SerialPollCoordinator.vhd] - Blame information for rev 13

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 3 Andrewski
--------------------------------------------------------------------------------
2 13 Andrewski
--This file is part of fpga_gpib_controller.
3
--
4
-- Fpga_gpib_controller is free software: you can redistribute it and/or modify
5
-- it under the terms of the GNU General Public License as published by
6
-- the Free Software Foundation, either version 3 of the License, or
7
-- (at your option) any later version.
8
--
9
-- Fpga_gpib_controller is distributed in the hope that it will be useful,
10
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
11
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
12
-- GNU General Public License for more details.
13
 
14
-- You should have received a copy of the GNU General Public License
15
-- along with Fpga_gpib_controller.  If not, see <http://www.gnu.org/licenses/>.
16
--------------------------------------------------------------------------------
17 3 Andrewski
-- Entity: SerialPollCoordinator
18
-- Date:2011-11-03  
19 13 Andrewski
-- Author: Andrzej Paluch
20 3 Andrewski
--
21
-- Description ${cursor}
22
--------------------------------------------------------------------------------
23
library ieee;
24
use ieee.std_logic_1164.all;
25
use ieee.std_logic_unsigned.all;
26
 
27
 
28
library ieee;
29
use ieee.std_logic_1164.all;
30
use ieee.std_logic_unsigned.all;
31
 
32
entity SerialPollCoordinator is
33
        port (
34
                -- clock
35
                clk : in std_logic;
36
                -- reset
37
                reset : in std_logic;
38
                -- data accepted
39
                DAC : in std_logic;
40
                -- receive status byte
41
                rec_stb : in std_logic;
42
                -- attention in
43
                ATN_in : in std_logic;
44
                -- attention out
45
                ATN_out : out std_logic;
46
                -- output valid in
47
                output_valid_in : in std_logic;
48
                -- output valid out
49
                output_valid_out : out std_logic;
50
                -- stb received
51
                stb_received : out std_logic
52
        );
53
end SerialPollCoordinator;
54
 
55
architecture arch of SerialPollCoordinator is
56
 
57
        -- serial poll coordinator states
58
        type SPC_STATE is (
59
                ST_IDLE,
60
                ST_WAIT_DAC,
61
                ST_WAIT_REC_STB_0
62
        );
63
 
64
        signal current_state : SPC_STATE;
65
 
66
begin
67
 
68
        ATN_out <= '0' when current_state = ST_WAIT_DAC else ATN_in;
69
        output_valid_out <= '0' when current_state = ST_WAIT_DAC else output_valid_in;
70
        stb_received <= '1' when current_state = ST_WAIT_REC_STB_0 else '0';
71
 
72
        process (clk, reset) begin
73
                if reset = '1' then
74
                        current_state <= ST_IDLE;
75
                elsif rising_edge(clk) then
76
                        case current_state is
77
                                when ST_IDLE =>
78
                                        if rec_stb='1' then
79
                                                current_state <= ST_WAIT_DAC;
80
                                        end if;
81
                                when ST_WAIT_DAC =>
82
                                        if DAC='1' then
83
                                                current_state <= ST_WAIT_REC_STB_0;
84
                                        elsif rec_stb='0' then
85
                                                current_state <= ST_IDLE;
86
                                        end if;
87
                                when ST_WAIT_REC_STB_0 =>
88
                                        if rec_stb='0' then
89
                                                current_state <= ST_IDLE;
90
                                        end if;
91
                                when others =>
92
                                        current_state <= ST_IDLE;
93
                        end case;
94
                end if;
95
        end process;
96
 
97
end arch;
98
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.