Subversion Repositories graphicsaccelerator

Release 13.1 par O.40d (lin)

Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved.

linux-i9em.site::  Tue May 17 19:22:04 2011

par -w -intstyle ise -ol high -t 1 VGA_Top_map.ncd VGA_Top.ncd VGA_Top.pcf

Constraints file: VGA_Top.pcf.

Loading device for application Rf_Device from file '3s200.nph' in environment /media/sda9/ISE_DS/ISE/.

   "VGA_Top" is an NCD, version 3.2, device xc3s200, package ft256, speed -5

Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)

Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)

INFO:Par:282 - No user timing constraints were detected or you have set the option to ignore timing constraints ("par

   -x"). Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of all

   internal clocks in this design. Because there are not defined timing requirements, a timing score will not be

   reported in the PAR report in this mode. The PAR timing summary will list the performance achieved for each clock.

   Note: For the fastest runtime, set the effort level to "std".  For best performance, set the effort level to "high".

Device speed data version:  "PRODUCTION 1.39 2011-02-03".

Device Utilization Summary:

   Number of BUFGMUXs                        2 out of 8      25%

   Number of External IOBs                  29 out of 173    16%

      Number of LOCed IOBs                  29 out of 29    100%

   Number of RAMB16s                         6 out of 12     50%

   Number of Slices                        504 out of 1920   26%

      Number of SLICEMs                      0 out of 960     0%

Overall effort level (-ol):   High

Placer effort level (-pl):    High

Placer cost table entry (-t): 1

Router effort level (-rl):    High

Starting initial Timing Analysis.  REAL time: 2 secs

Finished initial Timing Analysis.  REAL time: 2 secs

Starting Placer

Total REAL time at the beginning of Placer: 2 secs

Total CPU  time at the beginning of Placer: 1 secs

Phase 1.1  Initial Placement Analysis

Phase 1.1  Initial Placement Analysis (Checksum:962ecf22) REAL time: 3 secs

Phase 2.7  Design Feasibility Check

Phase 2.7  Design Feasibility Check (Checksum:962ecf22) REAL time: 3 secs

Phase 3.31  Local Placement Optimization

Phase 3.31  Local Placement Optimization (Checksum:962ecf22) REAL time: 3 secs

Phase 4.2  Initial Clock and IO Placement

Phase 4.2  Initial Clock and IO Placement (Checksum:23c362e2) REAL time: 3 secs

Phase 5.36  Local Placement Optimization

Phase 5.36  Local Placement Optimization (Checksum:23c362e2) REAL time: 3 secs

Phase 6.8  Global Placement

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Phase 6.8  Global Placement (Checksum:1fb7ff71) REAL time: 8 secs

Phase 7.5  Local Placement Optimization

Phase 7.5  Local Placement Optimization (Checksum:1fb7ff71) REAL time: 8 secs

Phase 8.18  Placement Optimization

Phase 8.18  Placement Optimization (Checksum:3d2812bc) REAL time: 10 secs

Phase 9.5  Local Placement Optimization

Phase 9.5  Local Placement Optimization (Checksum:3d2812bc) REAL time: 10 secs

Total REAL time to Placer completion: 10 secs

Total CPU  time to Placer completion: 9 secs

Writing design to file VGA_Top.ncd

Starting Router

Phase  1  : 3326 unrouted;      REAL time: 11 secs

Phase  2  : 3112 unrouted;      REAL time: 11 secs

Phase  3  : 1358 unrouted;      REAL time: 11 secs

Phase  4  : 1395 unrouted; (Par is working to improve performance)     REAL time: 12 secs

Phase  5  : 0 unrouted; (Par is working to improve performance)     REAL time: 16 secs

Updating file: VGA_Top.ncd with current fully routed design.

Phase  6  : 0 unrouted; (Par is working to improve performance)     REAL time: 17 secs

Phase  7  : 0 unrouted; (Par is working to improve performance)     REAL time: 34 secs

Phase  8  : 0 unrouted; (Par is working to improve performance)     REAL time: 34 secs

Phase  9  : 0 unrouted; (Par is working to improve performance)     REAL time: 35 secs

Total REAL time to Router completion: 35 secs

Total CPU time to Router completion: 33 secs

Partition Implementation Status

-------------------------------

  No Partitions were found in this design.

-------------------------------

Generating "PAR" statistics.

**************************

Generating Clock Report

**************************

+---------------------+--------------+------+------+------------+-------------+

|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|

+---------------------+--------------+------+------+------------+-------------+

|           Clk_BUFGP |      BUFGMUX0| No   |  142 |  0.003     |  0.883      |

+---------------------+--------------+------+------+------------+-------------+

|Inst_FreqDiv/counter |              |      |      |            |             |

|                <19> |      BUFGMUX3| No   |   20 |  0.001     |  0.882      |

+---------------------+--------------+------+------+------------+-------------+

* Net Skew is the difference between the minimum and maximum routing

only delays for the net. Note this is different from Clock Skew which

is reported in TRCE timing report. Clock Skew is the difference between

the minimum and maximum path delays which includes logic delays.

Timing Score: 0 (Setup: 0, Hold: 0)

Asterisk (*) preceding a constraint indicates it was not met.

   This may be due to a setup or hold violation.

----------------------------------------------------------------------------------------------------------

  Constraint                                |    Check    | Worst Case |  Best Case | Timing |   Timing

                                            |             |    Slack   | Achievable | Errors |    Score

----------------------------------------------------------------------------------------------------------

  Autotimespec constraint for clock net Clk | SETUP       |         N/A|    12.182ns|     N/A|           0

  _BUFGP                                    | HOLD        |     0.784ns|            |       0|           0

----------------------------------------------------------------------------------------------------------

  Autotimespec constraint for clock net Ins | SETUP       |         N/A|     5.263ns|     N/A|           0

  t_FreqDiv/counter<19>                     | HOLD        |     1.230ns|            |       0|           0

----------------------------------------------------------------------------------------------------------

All constraints were met.

INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the

   constraint is not analyzed due to the following: No paths covered by this

   constraint; Other constraints intersect with this constraint; or This

   constraint was disabled by a Path Tracing Control. Please run the Timespec

   Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 35 secs

Total CPU time to PAR completion: 33 secs

Peak Memory Usage:  131 MB

Placement: Completed - No errors found.

Routing: Completed - No errors found.

Number of error messages: 0

Number of warning messages: 0

Number of info messages: 1

Writing design to file VGA_Top.ncd

PAR done!