| 1 |
3 |
jaytang |
/**************************************
|
| 2 |
|
|
Author: J.W Tang
|
| 3 |
|
|
Email: jaytang1987@hotmail.com
|
| 4 |
|
|
Module: feature_accumulator
|
| 5 |
|
|
Date: 2016-04-24
|
| 6 |
|
|
|
| 7 |
|
|
Copyright (C) 2016 J.W. Tang
|
| 8 |
|
|
----------------------------
|
| 9 |
|
|
This file is part of LinkRunCCA.
|
| 10 |
|
|
|
| 11 |
|
|
LinkRunCCA is free software: you can redistribute it and/or modify
|
| 12 |
|
|
it under the terms of the GNU Lesser General Public License as
|
| 13 |
|
|
published by the Free Software Foundation, either version 3 of
|
| 14 |
|
|
the License, or (at your option) any later version.
|
| 15 |
|
|
|
| 16 |
|
|
LinkRunCCA is distributed in the hope that it will be useful,
|
| 17 |
|
|
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
| 18 |
|
|
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
| 19 |
|
|
GNU Lesser General Public License for more details.
|
| 20 |
|
|
|
| 21 |
|
|
You should have received a copy of the GNU Lesser General Public License
|
| 22 |
|
|
along with LinkRunCCA. If not, see <http://www.gnu.org/licenses/>.
|
| 23 |
|
|
|
| 24 |
|
|
By using LinkRunCCA in any or associated publication,
|
| 25 |
|
|
you agree to cite it as:
|
| 26 |
|
|
Tang, J. W., et al. "A linked list run-length-based single-pass
|
| 27 |
|
|
connected component analysis for real-time embedded hardware."
|
| 28 |
|
|
Journal of Real-Time Image Processing: 1-19. 2016.
|
| 29 |
|
|
doi:10.1007/s11554-016-0590-2.
|
| 30 |
|
|
|
| 31 |
|
|
***************************************/
|
| 32 |
|
|
|
| 33 |
2 |
jaytang |
module feature_accumulator(
|
| 34 |
|
|
clk,rst,datavalid,DAC,DMG,CLR,dp,d
|
| 35 |
|
|
);
|
| 36 |
|
|
|
| 37 |
|
|
parameter imwidth=512;
|
| 38 |
|
|
parameter imheight=512;
|
| 39 |
|
|
parameter x_bit=9;
|
| 40 |
|
|
parameter y_bit=9;
|
| 41 |
|
|
parameter address_bit=8;
|
| 42 |
|
|
parameter data_bit=38;
|
| 43 |
|
|
parameter latency=3; //latency to offset counter x, 3 if holes filling, else 1
|
| 44 |
|
|
parameter rstx=imwidth-latency;
|
| 45 |
|
|
parameter rsty=imheight-1;
|
| 46 |
|
|
parameter compx=imwidth-1;
|
| 47 |
|
|
input clk,rst,datavalid,DAC,DMG,CLR;
|
| 48 |
|
|
input [data_bit-1:0]dp;
|
| 49 |
|
|
output reg[data_bit-1:0]d;
|
| 50 |
|
|
|
| 51 |
|
|
////coordinate counter
|
| 52 |
|
|
reg [x_bit-1:0]x;
|
| 53 |
|
|
reg [y_bit-1:0]y;
|
| 54 |
|
|
always@(posedge clk or posedge rst)
|
| 55 |
|
|
if(rst)begin
|
| 56 |
|
|
x<=rstx[x_bit-1:0];y<=rsty[y_bit-1:0];
|
| 57 |
|
|
end
|
| 58 |
|
|
else if(datavalid)begin
|
| 59 |
|
|
if(x==compx[x_bit-1:0])begin
|
| 60 |
|
|
x<=0;
|
| 61 |
|
|
if(y==rsty[y_bit-1:0])
|
| 62 |
|
|
y<=0;
|
| 63 |
|
|
else y<=y+1;
|
| 64 |
|
|
end
|
| 65 |
|
|
else x<=x+1;
|
| 66 |
|
|
end
|
| 67 |
|
|
|
| 68 |
|
|
/////register d
|
| 69 |
|
|
wire [x_bit-1:0]minx,maxx,minx1,maxx1;
|
| 70 |
|
|
wire [y_bit-1:0]miny,maxy,miny1,maxy1;
|
| 71 |
|
|
//data accumulate
|
| 72 |
|
|
assign minx1=(DAC&(x<d[data_bit-1:data_bit-x_bit]))?x:d[data_bit-1:data_bit-x_bit];
|
| 73 |
|
|
assign maxx1=(DAC&(x>d[data_bit-x_bit-1:2*y_bit]))?x:d[data_bit-x_bit-1:2*y_bit];
|
| 74 |
|
|
assign miny1=(DAC&(y<d[2*y_bit-1:y_bit]))?y:d[2*y_bit-1:y_bit];
|
| 75 |
|
|
assign maxy1=(DAC&(y>d[y_bit-1:0]))?y:d[y_bit-1:0];
|
| 76 |
|
|
//data merge
|
| 77 |
|
|
assign minx=(DMG&(dp[data_bit-1:data_bit-x_bit]<minx1))?dp[data_bit-1:data_bit-x_bit]:minx1;
|
| 78 |
|
|
assign maxx=(DMG&(dp[data_bit-x_bit-1:2*y_bit]>maxx1))?dp[data_bit-x_bit-1:2*y_bit]:maxx1;
|
| 79 |
|
|
assign miny=(DMG&(dp[2*y_bit-1:y_bit]<miny1))?dp[2*y_bit-1:y_bit]:miny1;
|
| 80 |
|
|
assign maxy=(DMG&(dp[y_bit-1:0]>maxy1))?dp[y_bit-1:0]:maxy1;
|
| 81 |
|
|
|
| 82 |
|
|
always@(posedge clk or posedge rst)
|
| 83 |
|
|
if(rst)
|
| 84 |
|
|
d<={{x_bit{1'b1}},{x_bit{1'b0}},{y_bit{1'b1}},{y_bit{1'b0}}};
|
| 85 |
|
|
else if(datavalid)
|
| 86 |
|
|
if(CLR)
|
| 87 |
|
|
d<={{x_bit{1'b1}},{x_bit{1'b0}},{y_bit{1'b1}},{y_bit{1'b0}}}; //CLR
|
| 88 |
|
|
else d<={minx,maxx,miny,maxy};
|
| 89 |
|
|
|
| 90 |
|
|
endmodule
|
