OpenCores
URL https://opencores.org/ocsvn/m32632/m32632/trunk

Subversion Repositories m32632

[/] [m32632/] [trunk/] [rtl/] [DATENPFAD.v] - Blame information for rev 41

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 29 ns32kum
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
2 9 ns32kum
//
3
// This file is part of the M32632 project
4
// http://opencores.org/project,m32632
5
//
6 23 ns32kum
//      Filename:       DATENPFAD.v
7 29 ns32kum
//  Version:    3.0 Cache Interface reworked
8
//      History:        2.1 bug fix of 26 November 2016
9
//                              1.1 bug fix of 7 October 2015
10 23 ns32kum
//                              1.0 first release of 30 Mai 2015
11 29 ns32kum
//      Date:           2 December 2018
12 9 ns32kum
//
13 29 ns32kum
// Copyright (C) 2018 Udo Moeller
14 9 ns32kum
// 
15
// This source file may be used and distributed without 
16
// restriction provided that this copyright statement is not 
17
// removed from the file and that any derivative work contains 
18
// the original copyright notice and the associated disclaimer.
19
// 
20
// This source file is free software; you can redistribute it 
21
// and/or modify it under the terms of the GNU Lesser General 
22
// Public License as published by the Free Software Foundation;
23
// either version 2.1 of the License, or (at your option) any 
24
// later version. 
25
// 
26
// This source is distributed in the hope that it will be 
27
// useful, but WITHOUT ANY WARRANTY; without even the implied 
28
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR 
29
// PURPOSE. See the GNU Lesser General Public License for more 
30
// details. 
31
// 
32
// You should have received a copy of the GNU Lesser General 
33
// Public License along with this source; if not, download it 
34
// from http://www.opencores.org/lgpl.shtml 
35
// 
36 29 ns32kum
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
37 9 ns32kum
//
38
//      Modules contained in this file:
39
//      DATENPFAD       the data path of M32632
40
//
41 11 ns32kum
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
42 9 ns32kum
 
43 11 ns32kum
module DATENPFAD( BCLK, BRESET, WREN, IO_READY, LD_DIN, LD_IMME, WR_REG, IC_USER, ACC_FELD, ACC_STAT, DIN, DISP, IC_TEX,
44
                                  IMME_Q, INFO_AU, LD_OUT, DETOIP, MMU_UPDATE, OPER, PC_ARCHI, PC_ICACHE, RDAA, RDAB, START, WMASKE,
45 29 ns32kum
                                  WRADR, DONE, Y_INIT, WRITE_OUT, READ_OUT, ZTEST, RMW, QWATWO, ACC_DONE, CTRL_QW, PTB_SEL, PTB_WR, ACB_ZERO,
46 11 ns32kum
                                  ABORT, SAVE_PC, CFG, CINV, DP_Q, IVAR, MCR, PACKET, PC_NEW, PSR, SIZE, STRING, TRAPS, VADR, RWVFLAG,
47 9 ns32kum
                                  DBG_HIT, DBG_IN, COP_GO, COP_OP, COP_IN, COP_DONE, COP_OUT);
48
 
49
input                   BCLK;
50
input                   BRESET;
51
input                   WREN;           // write enable of the register file
52
input                   IO_READY;
53
input                   LD_DIN;
54
input                   LD_IMME;
55
input                   WR_REG;         // write signal for the DP_FPU
56
input                   IC_USER;
57
input                   RWVFLAG;
58
input   [14:0]   ACC_FELD;
59
input    [5:0]   ACC_STAT;
60
input   [31:0]   DIN;
61
input   [31:0]   DISP;
62
input    [2:0]   IC_TEX;
63
input   [31:0]   IMME_Q;
64
input    [6:0]   INFO_AU;
65
input    [1:0]   LD_OUT;
66
input   [12:0]   DETOIP;
67
input    [1:0]   MMU_UPDATE;
68
input   [10:0]   OPER;
69
input   [31:0]   PC_ARCHI;
70
input   [31:0]   PC_ICACHE;
71
input    [7:0]   RDAA;
72
input    [7:0]   RDAB;
73
input    [1:0]   START;
74
input    [1:0]   WMASKE;
75
input    [5:0]   WRADR;
76
input                   DBG_HIT;
77
input                   COP_DONE;
78
input   [23:0]   COP_OP;
79
input   [63:0]   COP_IN;
80
 
81
output                  DONE;
82
output                  Y_INIT;
83
output                  WRITE_OUT;
84
output                  READ_OUT;
85
output                  ZTEST;
86
output                  RMW;
87 12 ns32kum
output                  QWATWO;
88 9 ns32kum
output                  ACC_DONE;
89 29 ns32kum
output   [1:0]   CTRL_QW;
90 9 ns32kum
output                  PTB_SEL;
91
output                  PTB_WR;
92
output reg              ACB_ZERO;
93
output                  ABORT;
94
output                  SAVE_PC;
95
output  [12:0]   CFG;
96
output   [3:0]   CINV;
97
output  [63:0]   DP_Q;
98
output   [1:0]   IVAR;
99
output   [3:0]   MCR;
100
output   [3:0]   PACKET;
101
output  [31:0]   PC_NEW;
102
output  [11:0]   PSR;
103
output   [1:0]   SIZE;
104
output   [4:0]   STRING;
105
output   [5:0]   TRAPS;
106
output  [31:0]   VADR;
107
output  [40:2]  DBG_IN;
108
output                  COP_GO;
109
output [127:0]   COP_OUT;
110
 
111
reg     [31:0]   high_dq;
112 23 ns32kum
reg             [31:0]   IMMREG,MEMREG;
113 9 ns32kum
reg             [31:0]   BYDIN;          // the bypass register
114 23 ns32kum
reg                             LDIMR;
115 9 ns32kum
 
116
wire     [2:0]   BITSEL;
117
wire     [1:0]   BWD;
118
wire                    CLR_LSB;
119
wire    [31:0]   ERGEBNIS;       // the result bus
120
wire                    FL;
121
wire    [31:0]   FSR;
122 29 ns32kum
wire    [32:0]   MRESULT;
123 9 ns32kum
wire     [7:0]   OPCODE;
124
wire                    SELI_A;
125
wire                    SELI_B;
126
wire     [2:0]   SP_CMP;
127
wire    [31:0]   SRC1;           // the bus for the Source 1 operand
128
wire    [31:0]   SRC2;           // the bus for the Source 2 operand
129 23 ns32kum
wire    [31:0]   OUT_I;
130 9 ns32kum
wire     [4:0]   TT_DP;
131
wire                    TWREN;          // active if FPU Trap occurs
132
wire                    UP_DP;
133
wire                    WRADR_0;
134
wire                    WREN_L,WREN_LX;
135
wire                    LD_FSR;
136
wire                    UP_SP;
137
wire     [4:0]   TT_SP;
138
wire    [31:0]   addr_i;
139
wire     [2:0]   DP_CMP;
140
wire    [31:0]   DP_OUT;
141
wire    [31:0]   SFP_DAT;
142
wire     [6:0]   BMCODE;
143
wire    [31:0]   OUT_A,OUT_B;
144
wire                    SP_MUX;
145
wire    [31:0]   I_OUT;
146
wire    [31:0]   FP_OUT;
147
wire                    DOWR;
148
wire    [31:0]   DEST1,DEST2;
149
wire                    ENWR;
150
wire     [3:0]   OVF_BCD;
151
wire     [3:0]   DSR;
152
wire                    acb_zero_i;
153
wire    [31:0]   BMASKE;
154
 
155
assign  FL         = OPER[10];
156
assign  BWD        = OPER[9:8];
157
assign  OPCODE = OPER[7:0];
158
 
159
assign  ERGEBNIS = SP_MUX ? FP_OUT : I_OUT;
160
 
161 23 ns32kum
assign  WRADR_0 = WRADR[0] ^ CLR_LSB;
162 9 ns32kum
assign  ENWR = WREN_L | WREN;
163
assign  DOWR = ENWR & TWREN;
164
 
165
assign  WREN_L = WREN_LX & ~TRAPS[0];
166
 
167
assign  DP_Q[63:32] = high_dq;
168
 
169
assign  PC_NEW = SRC1;
170
 
171
always @(posedge BCLK) if (LD_OUT[1] || WREN)    ACB_ZERO <= acb_zero_i;
172
 
173 23 ns32kum
always @(posedge BCLK) if (LD_OUT[1]) high_dq <= ERGEBNIS;
174 9 ns32kum
 
175 23 ns32kum
always @(posedge BCLK)
176
        if (LD_DIN)
177
                begin
178
                        IMMREG <= IMME_Q;
179
                        MEMREG <= DIN;
180
                        LDIMR  <= LD_IMME;
181
                end
182
 
183
assign OUT_I = LDIMR ? IMMREG : MEMREG; // old solution had the multiplexor before the register
184 9 ns32kum
 
185
always @(posedge BCLK) if (RDAA[7]) BYDIN <= ERGEBNIS;
186
 
187 11 ns32kum
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
188 9 ns32kum
// Register Set 1 => SRC1
189 11 ns32kum
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
190 9 ns32kum
REGISTER        REG_SET_A(
191
        .BCLK(BCLK),
192
        .ENWR(ENWR),
193
        .DOWR(DOWR),
194
        .DIN(ERGEBNIS),
195
        .BYDIN(BYDIN),
196
        .RADR(RDAA),
197
        .WADR({WRADR[5:1],WRADR_0}),
198
        .WMASKE(WMASKE),
199
        .SELI(SELI_A),
200
        .DOUT(OUT_A));
201
 
202
assign SRC1 = SELI_A ? OUT_I : OUT_A;
203
 
204 11 ns32kum
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
205 9 ns32kum
// Register Set 2 => SRC2
206 11 ns32kum
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
207 9 ns32kum
REGISTER        REG_SET_B(
208
        .BCLK(BCLK),
209
        .ENWR(ENWR),
210
        .DOWR(DOWR),
211
        .DIN(ERGEBNIS),
212
        .BYDIN(BYDIN),
213
        .RADR(RDAB),
214
        .WADR({WRADR[5:1],WRADR_0}),
215
        .WMASKE(WMASKE),
216
        .SELI(SELI_B),
217
        .DOUT(OUT_B));
218
 
219
assign SRC2 = SELI_B ? OUT_I : OUT_B;
220
 
221 29 ns32kum
MULFILTER       M_FILTER(               // signed multiplier 32 * 32 bits = 64 bits
222 9 ns32kum
        .BWD(BWD),
223
        .SRC1(SRC1),
224
        .SRC2(SRC2),
225 29 ns32kum
        .MRESULT(MRESULT));
226 9 ns32kum
 
227
BITMASK  BITM_U(
228
        .AA(BMCODE),
229
        .DOUT(BMASKE));
230
 
231 11 ns32kum
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
232 9 ns32kum
// The integer data path
233 11 ns32kum
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
234 9 ns32kum
I_PFAD  GANZ_U(
235
        .FL(FL),
236
        .BRESET(BRESET),
237
        .BCLK(BCLK),
238
        .WREN(WREN),
239
        .LD_OUT(LD_OUT[1]),
240
        .ADDR(addr_i),
241
        .BITSEL(BITSEL),
242
        .BMASKE(BMASKE),
243
        .BWD(BWD),
244
        .DP_CMP(DP_CMP),
245
        .DP_OUT(DP_OUT),
246
        .FSR(FSR),
247
        .DETOIP(DETOIP[11:0]),
248
        .MRESULT(MRESULT),
249
        .OPCODE(OPCODE),
250
        .RDAA(RDAA),
251
        .SFP_DAT(SFP_DAT),
252
        .SP_CMP(SP_CMP),
253
        .SRC1(SRC1),
254
        .SRC2(SRC2),
255
        .WRADR(WRADR),
256
        .DSR(DSR),
257
        .OV_FLAG(TRAPS[2]),
258
        .ACB_ZERO(acb_zero_i),
259
        .BMCODE(BMCODE),
260
        .I_OUT(I_OUT),
261
        .PSR(PSR),
262
        .STRING(STRING),
263
        .OVF_BCD(OVF_BCD),
264
        .DISP(DISP[4:0]),
265
        .RWVFLAG(RWVFLAG));
266
 
267 11 ns32kum
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
268 9 ns32kum
// The address unit
269 11 ns32kum
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
270 9 ns32kum
ADDR_UNIT       ADDR_U(
271
        .BCLK(BCLK),
272
        .BRESET(BRESET),
273
        .IO_READY(IO_READY),
274
        .READ(ACC_FELD[11]),
275
        .WRITE(ACC_FELD[10]),
276
        .CLRMSW(ACC_FELD[2]),
277
        .FULLACC(ACC_FELD[8]),
278
        .POST(ACC_FELD[3]),
279
        .DISP_OK(INFO_AU[0]),
280
        .LDEA(ACC_FELD[9]),
281
        .NEWACC(ACC_FELD[14]),
282
        .FPU_TRAP(TRAPS[0]),
283
        .ADIVAR(INFO_AU[2]),
284
        .RWVAL_1(INFO_AU[3]),
285
        .ABO_STAT({INFO_AU[1],IC_USER}),
286
        .ACC_STAT(ACC_STAT),
287
        .ASIZE(ACC_FELD[13:12]),
288
        .BWD(BWD),
289
        .DISP(DISP),
290
        .IC_TEX(IC_TEX),
291
        .INDEX(ACC_FELD[7:4]),
292
        .MMU_UPDATE(MMU_UPDATE),
293
        .PC_ARCHI(PC_ARCHI),
294
        .PC_ICACHE(PC_ICACHE),
295
        .SRC1(SRC1),
296
        .SRC2(SRC2),
297
        .SRC2SEL(ACC_FELD[1:0]),
298 29 ns32kum
        .CTRL_QW(CTRL_QW),
299 9 ns32kum
        .ACC_DONE(ACC_DONE),
300
        .READ_OUT(READ_OUT),
301
        .WRITE_OUT(WRITE_OUT),
302
        .ABORT(ABORT),
303
        .ADDR(addr_i),
304
        .BITSEL(BITSEL),
305
        .PACKET(PACKET),
306
        .SIZE(SIZE),
307
        .VADR(VADR),
308
        .ZTEST(ZTEST),
309
        .RMW(RMW),
310 12 ns32kum
        .QWATWO(QWATWO),
311 9 ns32kum
        .OP_RMW(INFO_AU[4]),
312
        .PHASE_17(INFO_AU[5]),
313
        .NO_TRAP(INFO_AU[6]) );
314
 
315
CONFIG_REGS     CFG_DBG(
316
        .BCLK(BCLK),
317
        .BRESET(BRESET),
318
        .WREN(WREN),
319
        .LD_OUT(LD_OUT[1]),
320
        .OPCODE(OPCODE),
321
        .SRC1(SRC1),
322
        .WRADR(WRADR),
323
        .PTB_WR(PTB_WR),
324
        .PTB_SEL(PTB_SEL),
325
        .CFG(CFG),
326
        .CINV(CINV),
327
        .IVAR(IVAR),
328
        .Y_INIT(Y_INIT),
329
        .MCR(MCR),
330
        .DBG_TRAPS(TRAPS[5:3]),
331
        .PC_ARCHI(PC_ARCHI),
332
        .DSR(DSR),
333
        .USER(PSR[8]),
334
        .PCMATCH(DETOIP[12]),
335
        .DBG_IN(DBG_IN),
336
        .DBG_HIT(DBG_HIT),
337
        .READ(READ_OUT) );
338
 
339 11 ns32kum
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
340 9 ns32kum
// The long operation unit
341 11 ns32kum
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
342 9 ns32kum
DP_FPU  DOUBLE_U(
343
        .BCLK(BCLK),
344
        .FL(FL),
345
        .BRESET(BRESET),
346 23 ns32kum
        .LD_OUT(LD_OUT),
347 9 ns32kum
        .WR_REG(WR_REG),
348
        .BWD(BWD),
349
        .FSR(FSR[8:3]),
350
        .OPCODE(OPCODE),
351
        .SRC1(SRC1),
352
        .SRC2(SRC2),
353
        .START(START),
354
        .DONE(DONE),
355
        .UP_DP(UP_DP),
356
        .WREN_L(WREN_LX),
357
        .CLR_LSB(CLR_LSB),
358
        .DVZ_TRAP(TRAPS[1]),
359
        .DP_CMP(DP_CMP),
360
        .DP_OUT(DP_OUT),
361
        .DP_Q(DP_Q[31:0]),
362
        .TT_DP(TT_DP),
363
        .CY_IN(PSR[0]),
364
        .OVF_BCD(OVF_BCD),
365
        .COP_DONE(COP_DONE),
366
        .COP_OP(COP_OP),
367
        .COP_IN(COP_IN),
368
        .COP_GO(COP_GO),
369
        .COP_OUT(COP_OUT));
370
 
371 11 ns32kum
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
372 9 ns32kum
// The single precision floating point unit
373 11 ns32kum
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
374 9 ns32kum
SP_FPU  SINGLE_U(
375
        .FL(FL),
376
        .BCLK(BCLK),
377
        .BWD(BWD),
378
        .FSR(FSR[8:3]),
379
        .OPCODE(OPCODE),
380
        .SRC1(SRC1),
381
        .SRC2(SRC2),
382
        .LD_FSR(LD_FSR),
383
        .SP_MUX(SP_MUX),
384
        .UP_SP(UP_SP),
385
        .FP_OUT(FP_OUT),
386
        .I_OUT(SFP_DAT),
387
        .SP_CMP(SP_CMP),
388 23 ns32kum
        .TT_SP(TT_SP),
389 29 ns32kum
        .START(START[1]) );             // Aenderung
390 9 ns32kum
 
391
FP_STAT_REG     FPS_REG(
392
        .BCLK(BCLK),
393
        .BRESET(BRESET),
394
        .LFSR(LD_FSR),
395
        .WREN(ENWR),
396
        .WRADR(WRADR[5:4]),
397
        .UP_DP(UP_DP),
398 29 ns32kum
        .UP_SP(UP_SP),          // & LD_OUT[1]), Aenderung
399 9 ns32kum
        .DIN(SRC1[16:0]),
400
        .TT_DP(TT_DP),
401
        .TT_SP(TT_SP),
402
        .FPU_TRAP(TRAPS[0]),
403
        .TWREN(TWREN),
404
        .SAVE_PC(SAVE_PC),
405
        .FSR(FSR));
406
 
407
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.